• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.687-690
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• 2005

H.264/AVC에서 압축 효율을 향상시키기 위해 사용된 entropy coding중에 CABAC(Context-based Adaptive Binary Arithmetic Coding)은 하드웨어 복잡도가 높고 bit-serial 과정에서 data dependancy가 존재하기 때문에 빠른 연산이 어렵다. 본 논문에서는 adaptive arithmetic encoder와 정규화 과정을 효율적으로 구성하여 각 입력 심벌이 정규화 과정의 반복횟수에 관계없이 고정된 cycle에 encoding이 되도록 하였다. 제안한 구조는 pipeline으로 구성하기 용이하며, 이 경우 매 cycle에 한 입력 심벌의 encoding이 가능하다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.76-84
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• 1999

EZW proposed by Shapiro is based on a zerotree constructed in a way that a parent coefficient in a subband is related to four child coefficients in the next finer subband of similar orientation. This fixed treeing based on 1-to-4 parent-child is suitable to exploti hierachical correlations among subbands but not to exploit spatial correlations within a subband. A new treeing by Joo, et al. is suggested to simulatneously exploit those two correlatins by extending parent-child relationship in a flexible way. The flexible treeing leads to increasing the number of symbols and lowering entorpy comparing to the fixed treeing, and therefore a better compression can be resulted. In this paper, we suggest two techniques to suppress the increasing of symbols. First, a probing bit is generated to avoid redundant scan for insignivicant coefficients. Second, since all subbands do not always require the same kind of symbol-set, produced symbols are re-symbolized into binary codes according to a pre-defined procedure. Owing to those techniques, all symbols are generated as binary codes. The binary symbols can be entropy-coded by an adaptive arithmetic coding. Moerover, the binary symbol stream can give comparatively good performances without help of additional entropy coding. Our proposed coding scheme is suggested in two modes: binary coding mode and arithmetic coding mode. We evaluate the effectivenessof our modifications by comparing with the original EZW.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.82-91
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• 1996

In this paper, an image coding technique using fractal interpolation is proposed. Similar to the conventional methods, an image is partitioned into blocks and each block is coded independently. However, an interpolation point is ahsared by its neighboring blocks. This means that each block can use all its interpolation points with minimal increase of new data. For a simple implementation, triangular blocks are used instead of square blocks and new coefficients are difined. Data obtained in the encoding process hav estatistical characteristics suitable sfor entropy coding, an dthus arithmetic coding is perfomred for improving the compression efficiency. The results of the proposed coder in comparison with those of a conventional coder show that the interpolation method reduces block effect caused by a memoryless block coder, especially at low bit rates. This improvement is due to sharing of information between adjacent blocks. Moreover, th enumber of iteration required in ecoding process is reduced since more information is used to decode each block.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.88-96
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• 1994

In this paper, we propose a subband pyramid image coding scheme that uses ECVQ (ntropy Constrained Vector Quantizer). In subband pyramid image coding, each subband can be encoded with a coder matched to the statistics of that particular subband, and available versions of the original image at different resolution are easily obtained. ECVQ, aiming at the minimization of the distortion for a fixed entropy of the quantizer output, is well combined with the subband pyramid image coding which yields high compression ratio and good image quality. The optimum bit allocation to each subbands corresponds to the points where the individual distortion rate curves are of particular slope, weighted to the number of samples in that subband, in designing ECVQ.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4C
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• pp.541-549
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• 2004

In this paper, a new improved EREC based error resilient coding in JPEG-2000 standard is proposed, considering the error sensitive wireless environment with limited channel capacity. In order to apply EREC, we use the variable bit-rate by using R-D optimization. Simulation results demonstrate that the proposed EREC based error resilient coding is more resilient than the error resilient schemes used in JPEG-2000.

• Journal of Broadcast Engineering
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• v.12 no.4
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• pp.377-380
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• 2007

In this paper, an improved CABAC is proposed for the lossless compression in H.264/AVC. CABAC in the lossless coding is not as efficient as that in the lossy compression since it was developed for lossy coding. CABAC for the lossless coding in H.26과/AVC Advanced 4:4:4 Profile is applied without the change of the conventional binarization method. Thus, a binarization method considering the statistical characteristic of residual signals is proposed for the lossless coding in 0.264/AVC Advanced 4:4:4 Profile. The experimental results show that the proposed method obtains approximately 3.4% bitrate reduction in comparison to that of the conventional lossless coding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.42-49
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• 2007

CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.66-72
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• 2009

This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.