• Journal of IKEEE
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• v.22 no.4
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• pp.1006-1011
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• 2018

This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.38 no.6
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• pp.851-857
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• 2018

In this research, LCA analysis of the manufacturing process of pot bearing for fixed, movable in all directions, movable in one direction was carried out to analyze the environmental load using the LCA methodology. Especially, the water footprint that has been and issue in recent years was analyzed. As a result of LCA, it was analyzed that the contribution of the plate was more than 64.2% in all of the six impact categories in the case of fixed pot bearing base, and more than 94% in the category of resource depletion and photochemical oxidant creation. In the case of all direction pot bearing and one direction pot bearing, the contribution of PTFE was the highest in the global warming and stratospheric ozone depletion, and the contribution by the plate was higher in the other impact categories. The water footprint of each type of pot bearing was analyzed as $22.4m^3\;H_2O\;eq/kg$ for one direction pot bearing, $17.1m^3\;H_2O\;eq/kg$ for fixed pot bearing, and $14.1m^3\;H_2O\;eq/kg$ for all direction pot bearing. As a result of life cycle analysis, the contribution of water use in manufacturing was more than 65% in all three types. The results of this study can be used as basic data for decision making in construction method and material selection of bridges in the future.

• Journal of the Korean Society of Marine Environment & Safety
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• v.25 no.4
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• pp.468-475
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• 2019

An end-line flame arrester allows free venting in combination with flame protection for vertical vent applications. End-line flame arresters are employed in various fields, especially in shipping. In flame arresters, springs are essential parts because the spring load and the spring's elasticity determine the hood opening moment. In addition, the spring has to work under a high-temperature condition because of the burning gas flame. Therefore, it is necessary to analyze the mechanical load and elasticity of the spring when the flame starts to appear. Based on simulations of the working process of a specific end-line flame arrester, a thermal and structural analysis of the spring is performed. A three-dimensional model of a burned spring is built using computational fluid dynamics (CFD) simulation. Results of the CFD analysis are input into a finite element method simulation to analyze the spring structure. The research team focused on three cases of spring loads: 43, 93, and 56 kg, correspondingly, at 150 mm of spring deflection. Consequently, the spring load was reduced by 10 kg after 5 min under a $1,000^{\circ}C$ heat condition. The simulation results can be used to predict and estimate the spring's load and elasticity at the burning time variation. Moreover, the obtained outcome can provide the industry with references to optimize the design of the spring as well as that of the flame arrester.

• Journal of the Korea institute for structural maintenance and inspection
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• v.23 no.5
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• pp.84-95
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• 2019

This paper reports the process of seismic fragility analysis for the rahman-type continuous bridge system. The target structure was the five span highway bridge with maximum pier hight of 72m. OpenSees software was used for the nonlinear time history analysis. In this study, 50 ground motions are considered for nonlinear time history analysis. For each ground motion, PGA was scaled from 0.1g to 2.0g with intervals of 0.1g in order to consider a wide range of the seismic intensity measure. In addition, yield displacement and ultimate displacement of each pier were calculated through section analysis. Based on the result of non linear time history analysis and section analysis, damage condition of target bridge was classified according to the definition of damage condition proposed by Barbat et al. As a result, it was predicted that Extensive Damage occurred at P1 when 0.731 g earthquake occurred in the longitudinal direction. Based on the seismic fragility analysis results, it is found that the probability of occurrence of Extensive Damage in the 4,800 - year period earthquake was about 4.2%. Therefore the target bridge has enough safety for earthquake.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.595-598
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• 2014

In order to provide the Mobile Stations operating in IEEE 802.11 Wireless LAN network with seamless handover, a comprehensive study on the functions of handover considering various networking environments and characteristics of Mobile Stations is required. Note that the channel scan process finding a new AP takes the major portion of handover time, and this is the most significant issue with seamless handover for real-time multimedia service in WLAN environment. In this paper the functions required to provide seamless handover in IEEE 802.11 WLAN network are identified, and a new scanning technique is proposed with which the Mobile Stations can selectively scan the channels to reduce the channel scan time in various network environments. Here each Mobile Station awares of the channels the neighbor APs are using by scanning them in advance according to the proposed technique. Afterwards, when handover is actually required, the optimal AP is decided quickly by scanning only the predetemined group of channels and order of scan without unnecessary scan of all the channels. In addition, proposes to enter the Scan Trigger Value and Handover Threshold Value in mobile phones in order to prevent the phenomenon can not handover.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.3
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• pp.497-504
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• 2019

We fabricated $HfO_2$ thin films using RF magnetron sputtering method, and investigated structural and optical properties of $HfO_2$ thin films with RTA temperatures in $N_2$ ambient. $HfO_2$ thin films exhibited polycrystalline structure regardless of annealing process, FWHM of M (-111) showed reduction trend. The surface roughness showed the smallest of 3.454 nm at a annealing temperature of $600^{\circ}C$ in result of AFM. All $HfO_2$ thin films showed the transmittance of about 80% in visible light range. By fitting the refractive index from the transmittance and reflectance to the Sellmeir dispersion relation, we can predict the refractive index of the $HfO_2$ thin film according to the wavelength. The $HfO_2$ thin film annealed at $600^{\circ}C$ exhibited a high refractive index of 2.0223 (${\lambda}=632nm$) and an excellent packing factor of 0.963.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.755-758
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• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.565-568
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• 2014

This paper presents a 0.2V DC/DC boost converter with regulated output for thermoelectric energy harvesting. To use low voltages from a thermoelectric device, a start-up circuit consisting of native NMOS transistors and resistors boosts an internal VDD, and the boosted VDD is used to operate the internal control block. When the VDD reaches a predefined value, a detector circuit makes the start-up block turn off to minimize current consumption. The final boosted VSTO is achieved by alternately operating the sub-boost converter for VDD and the main boost converter for VSTO according to the comparator outputs. When the VSTO reaches 2.4V, a buck converter starts to operate to generate a stabilized output VOUT. Simulation results shows that the designed converter generates a regulated 1.8V output from an input voltage of 0.2V, and its maximum power efficiency is 60%. The chip designed using a $0.35{\mu}m$ CMOS process occupies $1.1mm{\times}1.0mm$ including pads.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.271-274
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• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.581-584
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• 2014

In this paper, a micro-scale photovoltaic(PV) energy harvesting system is proposed where an MPPT(Maximum Power Point Tracking) control is implemented using an energy distribution technique. Miniature PV cells output very low energy and low voltages, and thus, they cannot be used to directly power the MPPT controller. In the proposed system, a start-up circuit boosts an internal Vcp, and the boosted Vcp is used to operate the internal MPPT control block. When the Vcp reaches a predefined value, a detector circuit makes the start-up block turn off and provide a power converter with the energy from the PV cell. When the Vcp decreases such that the MPPT controller can not be operated, the energy transferred to the power converter is blocked and the start-up circuit is reactivated. In this way, the MPPT function is achieved by alternately operating the start-up circuit and the power converter using the energy distribution technique, and the harvested energy is transferred to a load through a PMU(Power Management Unit). The proposed circuit is designed in a 0.35um CMOS process and its functionality has been verified through extensive simulations. The designed chip area including pads is $1430um{\times}1110um$.