• IEIE Transactions on Smart Processing and Computing
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• v.5 no.6
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• pp.418-429
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• 2016

In this paper, we propose a hybrid Wyner-Ziv video coding structure that combines conventional motion predictive video coding and Wyner-Ziv video coding to eliminate the feedback channel, which is a major practical problem in applications using the Wyner-Ziv video coding approach. The proposed method divides a hybrid frame into two regions. One is coded by a motion predictive video coder, and the other by the Wyner-Ziv coding method. The proposed encoder estimates side information with low computational complexity, using the coding information of the motion predictive coded region, and estimates the number of syndrome bits required to decode the region. The decoder generates side information using the same method as the encoder, which also reduces the computational complexity in the decoder. Experimental results show that the proposed method can eliminate the feedback channel without incurring a significant rate-distortion performance loss.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.13-20
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• 2005

For Modern Consumer and Communication Elecronic Devices, Always Error Protecting HW and SW is used. The Core is RS(Reed Solomon) Codec in Galois Field GF($2^8$). Here New 2 to 3 Symbol RS Decoder Design and Encoder design Method using Normalized error position Value is described. Examples are given to show the methods are working well.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.237-240
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• 2001

MP3는 현재 디지털 오디오 압축 표준으로 널리 사용되고 있으며 12:1의 높은 압축률을 가진다. MP3 encoding의 경우 현재는 대부분 PC를 이용하고 있으므로 MP3 encoding과 decoding을 동시에 할 수 있는 칩이 나오면 이러한 불편함 없이 portable이 가능해지며 라디오, CD, 카세트 테이프 등으로부터 고음질 녹음 후 재생이 가능해진다. TMS320C30과 호환되는 DSP 코어를 이용하였으며 MP3 엔코딩과 디코딩 실시간 수행을 위하여 알고리즘 개선과 FFT block, 주변 interface block을 설계하였다. 최종적으로 MP3 encoder와 decoder 칩 설계하고 이를 하드웨어 에뮬레이션을 이용하여 검증하였다.

• Annual Conference on Human and Language Technology
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• 2016.10a
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• pp.263-267
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• 2016

채팅 시스템은 사람이 사용하는 언어로 컴퓨터와 의사소통을 하는 시스템이다. 최근 딥 러닝이 큰 화두가 되면서 다양한 채팅 시스템에 관한 연구가 빠르게 진행 되고 있다. 본 논문에서는 문장을 Recurrent Neural Network기반 의사형태소 분석기로 분리하고 Attention mechanism Encoder-Decoder Model의 입력으로 사용하는 채팅 시스템을 제안한다. 채팅 데이터를 통한 실험에서 사용자 문장이 짧은 경우는 답변이 잘 나오는 것을 확인하였으나 긴 문장에 대해서는 문법에 맞지 않는 문장이 생성되는 것을 알 수 있었다.

• Annual Conference on Human and Language Technology
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• 2016.10a
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• pp.134-138
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• 2016

정보의 양이 빠르게 증가함으로 인해 필요한 정보만을 효율적으로 얻기 위한 질의응답 시스템의 중요도가 늘어나고 있다. 그 중에서도 질의 문장에서 주어와 관계를 추출하여 정답을 찾는 지식베이스 기반 질의응답 시스템이 활발히 연구되고 있다. 그러나 기존 지식베이스 기반 질의응답 시스템은 하나의 질의 문장만을 사용하므로 정보가 부족한 단점이 있다. 본 논문에서는 이러한 단점을 해결하고자 정보검색을 통해 질의와 유사한 문장을 찾고 Recurrent Neural Encoder-Decoder에 검색된 문장과 질의를 함께 활용하여 주어와 관계를 찾는 모델을 제안한다. bAbI SimpleQuestions v2 데이터를 이용한 실험에서 제안 모델은 질의만 사용하여 주어와 관계를 찾는 모델보다 좋은 성능(정확도 주어:33.2%, 관계:56.4%)을 보였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.849-855
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• 1987

This paper describes an implementation of the absolute moment block truncation coding(AMBTC) in real time for the moving picture data compression. We have realized a system composed of the encoder and decoder, and operated it using an NTSC TV signal. The encoder consists of a 4-1line buffer memory and a data processing block. Besides, there are signal conditioner and a control signal generator. Experimental results show that the quality of the processed image with a data rate of 10Mb/s is slightly degraded, but not objectionable, comparing data rate of 80Mb/s.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.147-156
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• 1998

In this paper, an arithmetic processor using multi-valued logic is designed. For implementing of multi-valued logic circuits, we use current-mode CMOS circuits and design encoder which change binary voltage-mode signals to multi-valued current-mode signals and decoder which change results of arithmetic to binary voltage-mode signals. To reduce the number of partial product we use 4-radix SD number partial product generation algorithm that is an extension of the modified Booth's algorithm. We demonstrate the effectiveness of the proposed arithmetic circuits through SPICE simulation and Hardware emulation using FPGA chip.

• Journal of Korea Multimedia Society
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• v.7 no.5
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• pp.658-667
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• 2004

For digital image compression, various fractal image coding schemes using the self-similarity of image have been studied extensively. This paper discusses the problem that occurs during the calculating process of adaptive orthogonal transformation and provides improvements of LIFS coding scheme using the transformation. This proposed scheme has a better performance than JPEG for a wide range of compression ratio. This research also proposes an image composition method consisting of all domains of the transformation. The results show that the arithmetic operation processes of the encoder and the decoder become much smaller even without the distortion of the coding performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1506-1511
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• 2004

The error control of digital transmission system is a very important subject because of the noise effects, which is very sensitive to transmission performance of the digital communication system It employs a modified Euclid's algorithm to compute the error-location polynomial and error-magnitude polynomial of input data. The circuit size is reduced by selecting the Modified Euclid's Algorithm with one Euclid Cell of mutual operation. And the operation speed of Decoder is improved by using ROM and parallel structure. The proposed Encoder and Decoder are simulated with ModelSim and Active-HDL and synthesized with Synopsys. We can see that this chip is implemented on Xilinx Virtex2 XC2V3000. A share of slice is 28%. nut speed of this paper is 45Mhz.

• Smart Media Journal
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• v.2 no.2
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• pp.39-43
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• 2013

In this paper, we suggest a new technique for WPC parity-check matrix (H-matrix) generation and a corresponding decoding process. The key idea is to construct WPC H-matrix by using a convolutional encoder. It is easy to have many different coderates from a mother code with convolutional codes. However, it is difficult to have many different coderates with LDPC codes. Constructing LDPC Hmatrix based on a convolutional code can easily bring the advantage of convolutional codes to have different coderates. Moreover, both LDPC and convolutional decoding algorithms can be applied altogether in the decoding part. This process prevents the performance degradation of short-length WPC code.