• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.516-520
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• 2010

As the substantial increase in battlefield density, multiple and complex weapon system, Ensuring the Survivability of the platform has been emphasized. Most of platforms have equipped with ASE (Aircraft Survivability Equipment) system in order to take action against at modernized hostile weapon under current battlefield. ASE system enhance the survivability of the platform through providing accurate situation awareness information by detecting and countermeasuring hostile threats. One of Key factor of the AE system performance is handling multiple and complex threats. Multiple and complex threat emulation is an effective means of ASE system verification In this study, It discuss system verification method before installation by dealing with complex threat situation consists of individual threat.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.156-163
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• 1998

The ATM network provides ATM CES(Circuit Emulation Services) with AAL1 for CBR(constant bit rate) services such as telephone speech. In this study, quality assessment of telephone speech with CES over ATM was performed and discussed. For this, interoperability between ATM network and structured/unstructured DS1 link was modeled for simulation. And for qualiy assessment of telephone speech, SNR and MOS were used as an objective and a subjective measure, respectively. Experimental results have shown that MOS score 4 as well as SNR 30dB could be obtained at CLR of $10^{-3}$ or below for speech signal.

• International Journal of Advanced Culture Technology
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• v.10 no.4
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• pp.219-225
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• 2022

In November 1983, Deng Sanmu's wife, Zhang Jianquan, donated a large number of Deng Sanmu's original seal carving stones and seal cutting scores to the Heilongjiang Provincial Museum in China. Therefore, the Heilongjiang Provincial Museum of China is the richest and most authoritative place to collect Deng Sanmu's original seal cutting stones and seal carving scores. According to the fieldwork, the original seal cutting stones and the seal cutting score donated by Deng Sanmu's wife, Zhang Jianquan, include Deng Sanmu's seal cutting inscriptions made between 1922 and 1963. In addition, Deng Sanmu's own life and career in the art are documented in detail in his markings, so the seal cutting inscriptions of Deng Sanmu in the collection of the Heilongjiang Provincial Museum of China are quite representative. We paper is a documentary review and study of the seal inscriptions of Deng Sanmu in the collection of the Heilongjiang Provincial Museum in China. For the accuracy and richness of this study, a total of 89 representative seals in the collection are used as primary sources to study Deng Sanmu's seal cutting emulation method. The specific content is centered on ancient seals, Qin seals, and Han seals, from which the lineage of Deng Sanmu's emulation methods of seal cutting is further clarified.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.3B
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• pp.91-99
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• 2008

In this paper, we design the function of ULSLE(Upper Layer Shared LAN Emulation) to provide both the efficient LAN service and compatibility with 802.1D bridge in Hybrid two-stage AWG based WDM-PON. The ULSLE layer lies above MAC control layer in order to provide a mean to interface WDM-PON and 802.1D bridge. It also performs LAN emulation based on PON-Tag which is only used to decide both the transmission mode and the destination of frames transmitted from ONUs. That is, the PON-Tag is not used for downstream frames but destination address field in original frame instead. This decreases the processing overhead and complexity caused by PON-Tag at OLT and ONU. The verification of designed ULSLE is performed according to the specific scenarios based on transmission mode and destination using OPNET.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1007-1010
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• 2003

This paper presents in-circuit system-on-chip verification and debugging environment. To maximize the emulation speed, the software part is compiled natively for the host computer and the hardware part is mapped into FPGA. The two parts communicate with each other in transaction level. The operation of the hardware part and the software part is recorded independently during the emulation, and after the emulation is over, they are merged in a waveform to give user a unified view that covers both hardware and software.

• Journal of Communications and Networks
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• v.7 no.1
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• pp.1-12
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• 2005

Ethernet is being deployed in metropolitan area networks (MANs) as a lower-cost alternative to SONET-based infrastructures. MANs are usually required to support common communication services, such as voice and frame relay, based on legacy synchronous TDM technology in addition to asynchronous packet data transport. This paper addresses the clock synchronization problem that arises when transporting synchronous services over an asynchronous packet infrastructure, such as Ethernet. A novel algorithm for clock synchronization is presented combining time-stamp methods used in the network time protocol (NTP) with signal processing techniques applied to measured packet interarrival times. The algorithm achieves the frequency accuracy, stability, low drift, holdover performance, and rapid convergence required for viable emulation of TDM circuit services over Ethernet.

• The Korean Journal of Archival Studies
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• no.38
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• pp.265-309
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• 2013

In response to the current electronic record environment, storing electronic records for necessary long terms have been the topic of the times. Especially, the method to preserving original form such as original functional property and bit stream becomes the key to long term preservation of electronic records. Until now in Korea migration methods were chosen as long term preservation strategy for public records, but the limitations were that the functionality and the original bit stream could not be maintained. Among the strategies for long term preservation of electronic records, emulation has significant strengths in that it can replicate the original form of electronic records without changes in the bit stream, and that unlike migration it can establish a single preservation strategy without needing to apply individual strategies according to type of electronic record. Especially because it can replicate the functional components that cannot be implemented in the current long term preservation format, there is a need to study the application method based on the studies of electronic record types currently used by public institutions. This study, to explore the methods for applying emulation as a strategy for the long term preservation of electronic records, reviews the latest study cases from the west about emulation as base study, and tries to analyze the specific cases about the feasibility, target, and methods of emulation. Through this the study tries to explore the implications for domestic application as well as the strengths and weaknesses of emulation. To do this, the study analyses the concept, strengths and weaknesses of emulation as a long term preservation strategy, the analyses the latest best cases of emulation in the west; CAMiLEON, KB, Planets, and KEEP project. Based on these analysis this study tries to suggest implications and application methods for electronic records in the future in Korea.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.479-488
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• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.911-914
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• 2003

A logic design training kit with print port emulation function was developed. The input device of the kit was 4$\times$4 key input and 6 FND(DYNAMIC) and LCD were used as out put devices and the output device were also can controlled by PC connectde by print port to the kit. The emulator was coded by Visual Programming C++(MFC)

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.378-380
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• 2001

The railway signaling system consists of computerized vital devices. Therefor it is important to validate the required functions of developed signaling system. To verify the condition and functions of signaling functions, the plentiful laboratory test is required. To achieve this, the emulation S/W for signaling test-bench is needed. The object-oriented concept for trackside signaling equipments emulation is described in this paper.