• Proceedings of the Korea Multimedia Society Conference
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• 2004.05a
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• pp.362-365
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• 2004

현재의 다양한 산업용 대상기기 시스템들을 제어. 관리 하기위한 소프트웨어들은 특정 시스템만을 위하여 존재 해왔었다. 이것은 시스템의 하드웨어 종속적인 컴퓨팅 환경을 초래 하였으며, 이를 기반으로 하는 소프트웨어 개발뿐만 아니라 유지, 보수에도 많은 어려움이 뒤따르게 되었다. 본 논문에서는 하드웨어 독립적으로 소프트웨어 환경을 구성하여 이러한 어려움들을 극복하고자 한다 따라서 산업기기와 병행하여 사용 할 수 있는 플랫폼 독립적인 자바 기반의 임베디드 시스템을 제안하고, 산업기기의 진단ㆍ관리를 위한 시스템을 구현 하였다.

• Proceedings of the Korea Multimedia Society Conference
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• 2004.05a
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• pp.342-345
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• 2004

자바는 임베디드 시스템을 프로그램 하기에 매력적인 언어와 플랫폼으로 인식되어져 왔다. 그러나 잉베디드 자바의 메모리와 프로세서 한계점을 가지고 임베디드 자바에 표준 자바 클래스 파일을 적용하기에는 적당하지 않다. 본 논문에서는 타겟디바이스에서 바이트 코드를 수행하기 전에 심볼레퍼런스 정보를 실제 주소로 바꾸기 위해 프리레졸루션을 사용하여 실행시간을 줄일 수 있는 효율적인 메소드를 제안하였다. 클래스 파일에서 컨스턴트풀의 사이즈를 알기 위해서 13개의 클래스 파일들을 시험하였다. 본 프리레졸루션은 원래 사이즈의 92% 정도 전체적인 메모리 footprint를 줄였다. 또한, 메모리 참조 횟수도 감소시켰다.

• Journal of Korea Multimedia Society
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• v.8 no.12
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• pp.1649-1657
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• 2005

In this paper, a fast implementation of JPEG is discussed and its application to multimedia service is presented for mobile wireless internet. A fast JPEG player is developed based on several fast algorithms for mobile handset. In the color transformation, RCT is adopted instead of ICT for JPEG source. For the most time-consuming DCT part, the binDCT can reduce the decoding time. In upsampling and RGB conversion, the transformation from YCbCr to RGB 16 bit is made at one time. In some parts, assembly language is applied for high-speed. Also, an implementation of multimedia in mobile handset is described using MJPEG (Motion JPEG) and QCELP(Qualcomm Code Excited Linear Prediction Coding). MJPEG and QCELP are used for video and sound, which are synchronized in handset. For the play of MJPEG, the decoder is implemented as a S/W upon the MSM 5500 baseband chip using the fast JPEG decoder. For the play of QCELP, the embedded QCELP player in handset is used. The implemented multimedia player has a fast speed preserving the image quality.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.10
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• pp.4948-4967
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• 2017

On mobile devices, image sequences are widely used for multimedia applications such as computer vision, video enhancement, and augmented reality. However, the real-time processing of mobile devices is still a challenge because of constraints and demands for higher resolution images. Recently, heterogeneous computing methods that utilize both a central processing unit (CPU) and a graphics processing unit (GPU) have been researched to accelerate the image sequence processing. This paper deals with various optimizing techniques such as parallel processing by the CPU and GPU, distributed processing on the CPU, frame buffer object, and double buffering for parallel and/or distributed tasks. Using the optimizing techniques both individually and combined, several heterogeneous computing structures were implemented and their effectiveness were analyzed. The experimental results show that the heterogeneous computing facilitates executions up to 3.5 times faster than CPU-only processing.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.499-502
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• 1999

This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.327-330
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• 2008

This paper shows an implementation of WLAN-based Audio/Video(A/V) system for multimedia home networks. Proposed WLAN-based A/V system can transmit multimedia data of high quality. The entire system consists of a 16-bit RISC controller, a program ROM, a SRAM, timers, an interrupt controller, a DART, GPIOs, an I2C and the OFDM modem supporting for the IEEE 802.11g standard. The simple MAC functions are implemented by firmware on an embedded 16-bit RISC controller. The OFDM modem supports a complete set of data rates up to 54Mbps. Proposed the system is implemented by an Altera FPGA EP1S60F1020C6 device, a 10-bit 2-ch DAC, a 10-bit 2-ch ADC and RF/IF chips.

• Journal of Korea Multimedia Society
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• v.2 no.2
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• pp.155-165
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• 1999

Because the encrypted data is random, there is a possibility of threat that attacker reveals the secret data. On the other hand, as the image steganogrphy is to embed the secret data into cover image and to transmit the embedded image to receiver, an attacker could not know the existence of secret data even though he/she sees the embedded image, therefore the sender may reduce the threat of attack. In the image steganography, the secret data is embedded by modifying value of pixels as a form of noise. If the secret data is embedded into gray image, the degradation of image quality results from the modifications of image due to noise. Therefore many methods have been proposed to embed the secret data while dethering the gray image, but the existing method using error-diffusion has a problem that any patterns such as a diagonal lines or vertical take place due to embedding the secret data at the fixed interval. To solve this problem and to improve the existing method, we proposed the new method that embeds the secret data at changed point with respect to 1's run-length or at the position where has the minimum difference with the original dithered value. We evaluated the performance of the proposed method by computer simulation.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.917-923
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• 2011

In this paper, a new prediction based embedded compression (EC) codec algorithm for the JPEG2000 encoder system is proposed to reduce excessive memory requirements. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform (DWT) stages compared with direct implementation of the DWT engine of this paper. The LOCO-I predictor and MAP are widely used in many lossless picture compression codec. The proposed EC algorithm use these predictor which are very simple but surprisingly effective. The predictive EC scheme adopts a forward adaptive quantization and fixed length coding to encoding the prediction error. Simulation results show that our LOCO-I and MAP based EC codecs present only PSNR degradation of 0.48 and 0.26 dB in average, respectively. The proposed algorithm improves the average PSNR by 1.39 dB compared to the previous work in [9].

• Journal of Korea Multimedia Society
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• v.14 no.1
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• pp.76-84
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• 2011

Embedded Systems need to ensure real-time of the task response time depending on the applied fields of it. And task could be faulty due to various reasons in real time systems. Therefore in this paper, we design a task scheduler that guarantees deadlines of periodic tasks and considers a fault tolerance of defective task in embedded system with a single processor. In order to provide real-time, we classify tasks with periodic/aperiodic tasks and applies RMS(Rate Monotonic Scheduling) method to schedule periodic tasks and can guarantees execution of aperiodic tasks by managing surplus times obtained after analyzing the execution time of periodic tasks. In order to provide fault tolerance, we manage backup times and reexecute a fault task to restore it's conditions.

• Journal of Korea Multimedia Society
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• v.10 no.11
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• pp.1446-1459
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• 2007

This paper presents and analyzes a novel technique that makes it possible to improve the performance of low-end embedded systems through SoC(System-on-a-Chip) platform supporting dynamic cooperation between hardware and software modules. Traditional embedded systems with limited hardware resources have the poor capability of carrying out multi-tasking jobs including complex calculations. The proposed SoC platform, which provides dynamic cooperation between hardware and software modules, decomposes a single specific system into tasks for given system requirements. Additionally, we also propose a technique for efficient communication and synchronization between hardware and software tasks in cooperation with each other. Several experiments are conducted to illustrate the application and efficiency of the proposed SoC platform. They show that the proposed SoC platform outperforms the traditional embedded system, where only software tasks run, as the number of memory access is increased and the system become more complex.