• 대한임베디드공학회논문지
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• 제12권3호
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• pp.169-176
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• 2017

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

• 대한임베디드공학회논문지
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• 제9권1호
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• pp.17-24
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• 2014

In this paper, we implement and evaluate the performance of a vector-based rasterization algorithm for 3D graphics by using a SIMD (single instruction multiple data) many-core processor architecture. In addition, we evaluate the impact of a data-per-processing elements (DPE) ratio that is defined as the amount of data directly mapped to each processing element (PE) within many-core in terms of performance, energy efficiency, and area efficiency. For the experiment, we utilize seven different PE configurations by varying the DPE ratio (or the number PEs), which are implemented in the same 130 nm CMOS technology with a 500 MHz clock frequency. Experimental results indicate that the optimal PE configuration is achieved as the DPE ratio is in the range from 16,384 to 256 (or the number of PEs is in the range from 16 and 1,024), which meets the requirements of mobile devices in terms of the optimal performance and efficiency.

• 제어로봇시스템학회논문지
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• 제11권4호
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• pp.314-321
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• 2005

In this paper an intelligence embedding quadruped pet robot is described. It has 15 degrees of freedom and consists of various sensors such as CMOS image, voice recognition and sound localization, inclinometer, thermistor, real-time clock, tactile touch, PIR and IR to allows owners to interact with pet robot according to human's intention as well as the original features of pet animals. The architecture is flexible and adopts various embedded processors for handling sensors to provide modular structure. The pet robot is also used for additional purpose such like security, gaming visual tracking, and research platform. It is possible to generate various actions and behaviors and to download voice or music files to maintain a close relation of users. With cost-effective sensor, the pet robot is able to find its recharge station and recharge itself when its battery runs low. To facilitate programming of the robot, we support several development environments. Therefore, the developed system is a low-cost programmable entertainment robot platform.

• 전기학회논문지
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• 제63권1호
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• pp.85-91
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• 2014

As RFID is utilized more frequently and diversely in terms of its application areas, the application of mobile RFID technology, which integrates cellular networks and RFID, is highly anticipated. The growth and development of the RFID field has bolstered the development of mobile RFID chips to be embedded in mobile phones. Because mobile RFID chips are embedded in cell phones, limitations such as low power, small form factor, and costliness must be confronted. This study presents the design of a RFID digital baseband processor that is suitable for mobile readers. The RF analog component, which affects the baseband signals, is designed separately, in consideration of the limitations stated above. The function of the baseband processor was verified through simulations and prototyped using FPGA. The power consumption of the chip is 20mW under a 20MHz clock and the chip measures $3mm{\times}3mm$.

• 천문학회보
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• 제46권2호
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• pp.66.3-67
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• 2021

Low-mass stars form by the gravitational collapse of dense molecular cores. Observations and theories of low-mass protostars both suggest that accretion bursts happen in timescales of ~100 years with high accretion rates, so called episodic accretion. One mechanism that triggers accretion bursts is infalling fragments from the outer disk. Such fragmentation happens when the disk is massive enough, preferentially activated during the embedded phase of star formation (Class 0 and I). Most observations and models focus on the gas structure of the protostars undergoing episodic accretion. However, the dust and ice composition are poorly understood, but crucial to the chemical evolution through thermal and energetic processing via accretion burst. During the burst phase, the surrounding material is heated up, and the chemical compositions of gas and ice in the disk and envelope are altered by sublimation of icy molecules from grain surfaces. Such alterations leave imprints in the ice composition even when the temperature returns to the pre-burst level. Thus, chemical compositions of gas and ice retain the history of past bursts. Infrared spectral observations of the Spitzer and AKARI revealed a signature caused by substantial heating, toward many embedded protostars at the quiescent phase. We present the AKARI IRC 2.5-5.0 ㎛ spectra for embedded protostars to trace down the characteristics of accretion burst across the evolutionary stages. The ice compositions obtained from the absorption features therein are used as a clock to measure the timescale after the burst event, comparing the analyses of the gas component that traced the burst frequency using the different refreeze-out timescales. We discuss ice abundances, whose chemical change has been carved in the icy mantle, during the different timescales after the burst ends.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 1998년도 가을 학술발표논문집 Vol.25 No.2 (3)
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• pp.18-20
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• 1998

본 논문에서는 RISC Microprocessor Core 설계에 대한 기반 기술을 확립하여, GPS(Global Positioning System) 같은 Embedded 시스템 등에서 주로 사용되어 지고 있는 ARM사의 ARM7 CPU와 이진 호환이 가능한 Microprocessor를 설계하고자 하였다. 이를 위하여 RISC Microprocessor의 기본적인 구조를 바탕으로 하여 ARM7 CPU와의 호환을 위하여 ARM7 CPU의 명령어들이 주어진 Clock안에 수행될 수 있도록 설계를 하였고, 여러 모듈을 원활히 공유할 수 있도록 내부에 공유 버스를 설계하였다. 설계를 위해서 Verilog-HDL(Hardware Description Language)을 사용하였으며, Microprocessor를 기술하는데 있어서 Behavioral 구조와 RTL(Register Transfer Level) 구조를 혼합하여 사용하였다. 설계된 Microprocessor의 동작은 면적과 타이밍의 최적화를 거친 후 Cwaves 툴을 사용하여 실질적인 ARM7의 명령어들을 수행하면서 검증하였다.

• The Journal of the Acoustical Society of Korea
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• 제15권2E호
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• pp.24-32
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• 1996

A rigorous theory for modeling, analysis, optimum nonseparable filter bank in multidimensional M-band quantized subband codec are developed in this paper. Each pdf-optimized quantizer is modeled by a nonlinear gain-plus-additive uncorrelated noise and embedded into the subband structure. We then decompose the analysis/synthesis filter banks into their polyphase components and shift the down-and up-samplers to the right and left of the analysis/synthesis polyphase matrices respectively. Focusing on the slow clock rate signal between the samplers, we derive the exact expression for the output mean square quantization error by using spatial-invariant analysis. We show that this error can be represented by two uncorrelated components : a distortion component due to the quantizer gain, and a random noise component due to fictitious uncorrelated noise at the uantizer. This mean square error is then minimized subject to perfect reconstruction (PR) constraints and the total bit allocation for the entire filter bank. The algorithm gives filter coefficients and subband bit allocations. Numerical design example for the optimum nonseparable orthonormal filter bank is given with a quincunx subsampling lattice.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.1787-1790
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• 2003

In this paper. we proposed a hardware(H/W) structure which can compress the video and embed the watermark in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. The global operations of the designed H/W consists of the image compression with the watermarking and the reconstruction, and the watermarking operation is concurrently operated with the image compression. The implemented H/W used the 59％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70㎒ clock frequency over. So we verified the real time operation, 60 fields/sec(30 frames/sec).

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.817-824
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• 2016

A simultaneous bidirectional transceiver over a single wire has been developed in a 65 nm CMOS technology for a command and control bus. The echo signals of the simultaneous bidirectional link are cancelled by controlling the decision level of receiver comparators without power-hungry operational amplifier (op-amp) based circuits. With the clock information embedded in the rising edges of the signals sent from the source side to the sink side, the data is recovered by an open-loop digital circuit with 20 times blind oversampling. The data rate of the simultaneous bidirectional transceiver in each direction is 75 Mbps and therefore the overall signaling bandwidth is 150 Mbps. The measured energy efficiency of the transceiver is 56.7 pJ/b and the bit-error-rate (BER) is less than $10^{-12}$ with $2^7-1$ pseudo-random binary sequence (PRBS) pattern for both signaling directions.

• ETRI Journal
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• 제41권6호
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• pp.863-872
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• 2019

Elliptic curve cryptography is a relatively lightweight public-key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low-end IoT processors (ie, 8-bit AVR and 16-bit MSP processors). In particular, the three-level and two-level subtractive Karatsuba algorithms are adopted for multi-precision multiplication on AVR and MSP processors, respectively, and two-level Karatsuba routines are employed for multi-precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat-based inversion operations are used to mitigate side-channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.