• Journal of KIISE:Computing Practices and Letters
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• v.14 no.7
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• pp.625-635
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• 2008

Portable multimedia players have some different properties compared to general multimedia file server. Some of those properties are single user ownership, relatively low hardware performance, I/O burst by user special functions, and short software development cycles. Though suitable for processing multiple user requests at a time, the general multimedia file systems are not efficient for special user functions such as fast forwards/backwards. Soml' methods has been proposed to improve the performance and functionality, which the application programs give prediction hints to the file system. Unfortunately, they require the modification of all applications and recompilation. In this paper, we present a file system that efficiently supports user special functions in embedded multimedia systems using file block allocation, buffer-cache, and prefetch. A prefetch algorithm, SPRA (SPeed-based PRefetch Algorithm) predicts the next block using I/O patterns instead of hints from applications and it is resident in the file system, so doesn't affect application development process. From the experimental file system implementation and comparison with Linux readahead-based algorithms, the proposed system shows $4.29%{\sim}52.63%$ turnaround time and 1.01 to 3,09 times throughput in average.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.12
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• pp.1217-1222
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• 2010

This paper describes the Model-Based Development(MBD) process behind the flight control software of a close-range unmanned aerial vehicle(KUS-9). An integrated development environment was created using a commercial tool(MATLAB $Simulink^{(R)}$), which was utilized to design models for linear/nonlinear simulation, flight control law, operational logic and HILS(Hardware In the Loop Simulation) system. Software requirements were validated through flight simulations and peer reviews during the design process, whereas the models were verified through the application of a DO-178B verification tool. The integrity of automatically generated C code was verified by using a separate S/W testing tool. The finished software product was embedded on two different types of hardware and real-time operating system(uC/OS-II, VxWorks) to perform HILS and flight tests. The key findings of this study are that MBD Technology enables the development of a reusable and an extensible software product and auto-code generation technology allows the production of a highly reliable flight control software under a compressed time schedule.

• Journal of Energy Engineering
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• v.19 no.2
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• pp.128-135
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• 2010

This paper introduces step by step procedures for the fabrication and operation of an embedded solar tracker. The system presented consists of application software, compactRIO, C-series interface module, analogue input module, step drive, step motor, feedback devices and other accessories to support its functional stability. CompactRIO that has a real-tim processor allows the solar tracker to be a stand-alone real time system which operates automatically without any external control. An astronomical method and an optical method were used for a high-precision solar tracker. CdS sensors are used to constantly generate feedback signals to the controller, which allow a solar tracker to track the sun even under adverse conditions. The database of solar position and sunrise and sunset time was compared with those of those of the Astronomical Applications Department of the U.S. Naval Observatory. The results presented here clearly demonstrate the high-accuracy of the present system in solar tracking, which are applicable to many existing solar systems.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.1
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• pp.35-42
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• 2010

Guest operating systems running over the virtual machines share a variety of resources. Since CPU is allocated in a time division manner it consequently leads them to having the unknown physical time. It is not regarded as a serious problem in the server virtualization fields. However, it becomes critical in embedded systems because it prevents guest OS from executing real time tasks when it does not occupy CPU. In this paper we propose a hypercall to register a timer service to notify the timer request related real time. It enables hypervisor to schedule a virtual machine which has real time tasks to execute, and allows guest OS to take CPU on time to support real time. The following experiment shows its implementation on Xen-Arm and para-virtualized Linux. We also analyze the real time performance with response time of test application and frames per second of Mplayer.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.819-833
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• 2005

Code size reduction is ever becoming more important for compilers targeting embedded processors because these processors are often severely limited by storage constraints and thus the reduced code size can have a positively significant Impact on their performance. Various code size reduction techniques have different motivations and a variety of application contexts utilizing special hardware features of their target processors. In this work, we propose a novel technique that fully utilizes a set of hardware instructions, called the multiple load/store (MLS), that are specially featured for reducing code size by minimizing the number of memory operations in the code. To take advantage of this feature, many microprocessors support the MLS instructions, whereas no existing compilers fully exploit the potential benefit of these instructions but only use them for some limited cases. This is mainly because optimizing memory accesses with MLS instructions for general cases is an NP-hard problem that necessitates complex assignments of registers and memory off-sets for variables in a stack frame. Our technique uses a couple of heuristics to efficiently handle this problem in a polynomial time bound.

• KIISE Transactions on Computing Practices
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• v.23 no.1
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• pp.13-27
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• 2017

This paper presents a tool that automatically generates mobile web applications from user interface (UI) models which are based on PELUM (Pattern and Event based Logical User Interface Modeling). PELUM is a method for the effective development of UI-centered embedded systems via UI modeling. The proposed tool consists of a model editor and a code generator. The former provides an environment for modeling a Logical UI Model (LUM) and a Programming Interface Model (PIM) on the web. On the other hand, the code generator sets the screen configuration and events' behavior, according to the LUM, synthesizing a local database schema according to the PIM, and then generates an executable mobile web app. It also can produce mashup web apps by receiving an open API address via the PIM. The generated mobile web apps follow the Model-View-Controller (MVC) architecture in order for users to easily customize them. The proposed tool enables them to generate mobile web apps that can be executed on various devices by modeling logical UIs on the web.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.87-96
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• 2019

Low power issue is one of the most critical problems in the Internet of Things (IoT), which are powered by battery. To solve this problem, various approaches have been presented so far. In this paper, we propose a method to reduce the power consumption by reducing the numbers of accesses into the flash memory consuming a large amount of power for on-chip software execution. Our approach is based on using cooperative logging structure to distribute the sampling overhead in single sensor node to adjacent nodes in case of rare-event applications. The proposed algorithm to identify event occurrence is newly introduced with negative feedback method by observing difference between past data and recent data coming from the sensor. When an event with need of flash access is determined, the proposed approach only allows access to write the sampled data in flash memory. The proposed event detection algorithm (EDA) result in 30% reduction of power consumption compared to the conventional flash write scheme for all cases of event. The sampled data from the sensor is first traced into the random access memory (RAM), and write access to the flash memory is delayed until the page buffer of the on-chip flash memory controller in the micro controller unit (MCU) is full of the numbers of the traced data, thereby reducing the frequency of accessing flash memory. This technique additionally reduces power consumption by 40% compared to flash-write all data. By sharing the sampling information via LoRa channel, the overhead in sampling data is distributed, to reduce the sampling load on each node, so that the 66% reduction of total power consumption is achieved in several IoT edge nodes by removing the sampling operation of duplicated data.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.3
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• pp.623-628
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• 2009

The emergence of compact and low-power wireless communication sensors and actuators in the technology supporting the ongoing miniaturization of processing and storage allows for entirely the new kinds of embedded systems. These systems are distributed and deployed in environments where they may have been designed into a particular control method, and are often very dynamic. Collection of devices can communicate to achieve a higher level of coordinated behavior. Wireless sensor nodes deposited in various places provide light, temperature, and activity measurements. Wireless sensor nodes attached to circuits or appliances sense the current or control the usage. Together they form a dynamic and multi-hop routing network connecting each node to more powerful networks and processing resources. Wireless sensor networks are a specific-application and therefore they have to involve both software and hardware. They also use protocols that relate to both applications and the wireless network. Wireless sensor networks are consumer devices supporting multimedia applications such as personal digital assistants, network computers, and mobile communication devices. Wireless sensor networks are becoming an important part of industrial and military applications. The characteristics of modem embedded systems are the capable of communicating adapting the different operating environments. In this paper, We designed and implemented sensor network system which shows through host PC sensing temperature and humidity data transmitted for wireless sensor nodes composed wireless temperature and humidity sensor and designs sensor nodes using embedded system with the intention of studying USN.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.3
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• pp.111-117
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• 2018

Heterogeneous multi-core environment integrated with different functional cores is the powerful tool for the embedded system that became more complex and diverse. Specialized application requires one chip solution with different operating system over different cores. But this heterogeneity causes difficult configuration of the development environment, makes hard to develop and test software. We show the environment of heterogeneous multi-core processing can be mapped to symmetric multi-core environment. We construct Linux based RPMsg for the data exchange between processes similar with the heterogeneous multi-core RPMsg and experiment that the proposed environment can be used to reduce the steps of the heterogeneous multi-core application development. With this simplification, we suggest simulation method for easy development and debugging the heterogeneous multicore environment that makes complex steps to simple.