• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.917-920
• /
• 2005

This paper presents 3D graphics geometry processor for mobile applications. Geometry stage needs to cope with the large amount of computation. Geometry stage consists of transformation process and lighting process. To deal with computation in geometry stage, the vector processor that is based on pipeline chaining is proposed. The performance of proposed 3D graphics geometry processor is up to 4.3M vertex/sec at 100 MHz. Also, the designed processor is compliant with OpenGL ES that is widely used for standard API of embedded system. The proposed structure can be efficiently used in 3D graphics accelerator for mobile applications.

• Journal of the Institute of Convergence Signal Processing
• /
• v.6 no.4
• /
• pp.169-175
• /
• 2005

In recent, implementation of the embedded system is gradually in the spotlight of world-wide by information technology(IT) engineers. By this time, an implementation of real time system is limited on image acquisition and processing system in practical. In this paper, the USB camera interface system based on the embedded linux OS is implemented using USB 2.0 camera with low cost. This system can obtain image signals into the memory via X-hyper255B processor from USB camera. It is need to initialize USB camera by the Video4Linux for the kernel device driver. From the system image capturing and image processing can be performed. It is confirmed that the image data can be transformed to packet of Network File System(NFS) and connected to the internetwork, then the data can be monitored from the client computer connected to the internetwork.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.20 no.4
• /
• pp.580-585
• /
• 2010

In this paper, The object Tracking System is designed by SOPC based Nios II embedded processor and C2H compiler. And this system using single PTZ camera can effectively control IPs in the platform of SOPC based Nios II Embedded Processor and creating IP by C2H(C-To-Hardware) compiler for image-in/output, image-processing and devices of communication that can supply various monitoring information to network or serial. Accordingly, Special quality and processing speed of object tracking using high-quality algorism in the system is improved by hardware/software programming methods.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.7
• /
• pp.822-828
• /
• 2019

An Augmented Reality(AR) provides virtual information with a real environment, and the processor needs to access the memory for the AR system. However, the processor has the heavy workload as the technology improvement leads to increase the size of data. We need a specific module to reduce the workload to overcome the limitation. In this paper, we propose a Direct Memory Access(DMA) controller displaying image instead of the processor. We implemented the proposed DMA controller on a Field Programmable Gate Array(FPGA) and demonstrated the functionality of the DMA controller based on an Avalon Memory Mapped(Avalon-MM) interface. Also, the DMA controller is fabricated by using Magnachip/Hynix 0.35um CMOS technology and verified the feasibility of the embedded system.

• Journal of Internet Computing and Services
• /
• v.21 no.5
• /
• pp.149-157
• /
• 2020

Recently, as interest in artificial intelligence has increased, many studies have been conducted to implement AI processors. However, the AI processor requires functional verification as well as performance verification on whether the AI processor is suitable for the application. In this paper, We propose an AI processor performance analyzer that can verify the application performance and explore the limitations of the processor. By Using the performance analyzer, we explore the limitations of the AI processor and optimize the AI model to fit an AI processor in image recognition and speech recognition applications.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.04a
• /
• pp.46-49
• /
• 2011

This paper is to implement MoIP platform to send and receive video and audio at the same time by using high-performance Dual Core Processor. Even if Wall-Pad key component of a home network system is released by using embedded processors, it's lacking of performance in terms of multimedia processing and feature of video telephony through which video and voice are exchanged simultaneously. The main reason could be that embedded processors currently being used do not provide enough performance to support both MoIP call features and various home network features simultaneously. In order to solve these problems, Dual processor could be used, but in the other hands it brings another disadvantage of high cost. Therefore, this study is to solve the home automation features and video telephony features by using Dual Core Processor based on ARM 11 Processor and implement the MoIP Wall-Pad which can reduce the board design costs and component costs, and improve performance. The platform designed and implemented in this paper verified performance of MoIP to exchange the video and voice at the same time under the situation of Ethernet network.

• The KIPS Transactions:PartA
• /
• v.16A no.6
• /
• pp.473-480
• /
• 2009

This paper is to enhance a color image running in the PXA255 ARM processor based on embedded linux environments. Retinex is one of the representative algorithm for image enhancement in the previous research. However, retinex is not suitable the run on the embedded system because of its long processing time. So, we proposed the image enhancement algorithm for embedded system, with less quantity of operation and the effect equivalent to retinex. To achieve this goal, we propose and implement the image enhancement algorithm, which utilizes the image formation model and gamma correction to be effective in a back-light and dark image. The proposed algorithm converts the color space from RGB to HSV, and then V and S channels are processed. In order to optimize the proposed method in the PXA255 ARM processor, quantity of calculation is reduced. The performance of the proposed algorithm was evaluated through qualitative method and quantitative method. The results show that brightness and contrast are improved with less quantity of operation.

• The KIPS Transactions:PartA
• /
• v.12A no.5 s.95
• /
• pp.365-374
• /
• 2005

Schedulability analysis is necessary to build reliable embedded real-time systems. For schedulability analysis, worst-case execution time(WCET) analysis that computes upper bounds of the execution times of tasks, is required indispensably. WCET analysis is done in two phases. The first phase is high-level analysis that analyzes control flow and finds longest paths of the program. The second phase is low-level analysis that computes execution cycles of basic blocks taking into account the hardware architecture. In this thesis, we design and implement integrated WCET analysis tools. We develop the WCET analysis tools for XScale-based system called WATER(WCET Analysis Tool for Embedded Real-time system). WATER consist of high-level flow analyzer and low-level execution time analyzer. Also, We compare real measurement for execution of program with analysis result calculated by WATER.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.1
• /
• pp.148-155
• /
• 2006

Portable embedded systems which mainly handle multimedia applications involve the problem that frequent accesses to fetch data from memory make running time increased. To cope with the problem, embedded processors have adopted data prefetching schemes. From a power point of view, which is a main performance indicator of embedded systems, this paper analyzed to investigate how data prefetching schemes influence on system's performance. To solve the problem, we proposed a power-consumption analysis model of a memory system with data prefetching scheme and measured the power dissipated during running application programs. As a result data prefetching schemes have application program's running time reduced but have system's power increased. Also we proposed a performance analysis model considering execution time and power consumption for embedded system with data prefetching schemes.

• Journal of KIISE:Computing Practices and Letters
• /
• v.13 no.7
• /
• pp.454-461
• /
• 2007

Portable embedded systems have recently become smaller in size and offer a variety of junctions for users. These systems require high performance processors to handle the many functions and also a small battery to fit inside the system. However, due to its size, the battery life has become a major issue. It is important to have both efficient power design and management for each function, while optimizing processor voltage and clock frequency in order to extend the battery life of the system. In this paper, we calculated the efficiency of power in optimizing power rail. This system has two microprocessors. One is used to play music and movie files while the other is for DMB. In order to reduce power consumption, the DMB microprocessor is turned of while music or videos are played. Lastly, DVFS is applied to the processor in the system to reduce power consumption. Experimental results of the implemented system have resulted in reduced power consumption.