• Journal of Sensor Science and Technology
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• v.30 no.1
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• pp.20-24
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• 2021

The electrocardiogram (ECG) is one of the most extensively employed signals used to diagnose and predict cardiovascular diseases (CVDs). In recent years, several deep learning (DL) models have been proposed to improve detection accuracy. Among these, deep neural networks (DNNs) are the most popular, wherein the features are extracted automatically. Despite the increment in classification accuracy, DL models require exorbitant computational resources and power. This causes the mapping of DNNs to be slow; in addition, the mapping is challenging for a wearable device. Embedded systems have constrained power and memory resources. Therefore full-precision DNNs are not easily deployable on devices. To make the neural network faster and more power-efficient, spiking neural networks (SNNs) have been introduced for fewer operations and less complex hardware resources. However, the conventional SNN has low accuracy and high computational cost. Therefore, this paper proposes a new binarized SNN which modifies the synaptic weights of SNN constraining it to be binary (+1 and -1). In the simulation results, this paper compares the DL models and SNNs and evaluates which model is optimal for ECG classification. Although there is a slight compromise in accuracy, the latter proves to be energy-efficient.

• International Journal of Contents
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• v.18 no.2
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• pp.68-80
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• 2022

The health of the human heart is commonly measured using ECG (Electrocardiography) signals. To identify any anomaly in the human heart, the time-sequence of ECG signals is examined manually by a cardiologist or cardiac electrophysiologist. Lightweight anomaly detection on ECG signals in an embedded system is expected to be popular in the near future, because of the increasing number of heart disease symptoms. Some previous research uses deep learning networks such as LSTM and BiLSTM to detect anomaly signals without any handcrafted feature. Unfortunately, lightweight LSTMs show low precision and heavy LSTMs require heavy computing powers and volumes of labeled dataset for symptom classification. This paper proposes an ECG anomaly detection system based on two level BiLSTM for acceptable precision with lightweight networks, which is lightweight and usable at home. Also, this paper presents a new threshold technique which considers statistics of the current ECG pattern. This paper's proposed model with BiLSTM detects ECG signal anomaly in 0.467 ~ 1.0 F₁ score, compared to 0.426 ~ 0.978 F₁ score of the similar model with LSTM except one highly noisy dataset.

• Journal of the Korea Society of Computer and Information
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• v.14 no.4
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• pp.39-46
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• 2009

Many lip region detection methods have been developed in PC environment. But the existing methods are difficult to run on real-time in resource limited mobile devices. To solve the problem, this paper proposes a real-time lip region detection method for lipreading in Mobile device. It detects face region by using adaptive face color information. After that, it detects lip region by using geometrical relation between eyes and lips. The proposed method is implemented in a smart phone with Intel PXA 270 embedded processor and 386MB memory. Experimental results show that the proposed method runs at the speed 9.5 frame/see and the correct detection rate was 98.8% for 574 images.

• Nuclear Engineering and Technology
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• v.56 no.5
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• pp.1836-1844
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• 2024

The use of digital systems in radiation science has been increased last years in the different knowledge areas, as a detectors, spectrometry, spectroscopy, simulation, etc. This manuscript presents the design and implementation of a low-cost, fully portable multi-channel analyzer for nuclear spectrometry (in situ). The development is based on a 32-bit microcontroller with ARM Cortex-M7, this design is able to digitize and analyze pulses from a radiation detector without the need to transform the input signal with some filter, obtains the maximum height of each of the digitized pulses, segmenting the information into channels to form a histogram and visualizing the LCD screen incorporated in the system. A continuous digitization methodology was used, which is in charge of the DMA and an ADC with a resolution of 12 bits at a speed of 3.6 MSPS. The system has a compact design and can open and save spectra in an SD memory built into the system. The MCA in MCU was tested with a NaI(Tl) Scintillation radiation detector, which allowed us to determine that the spectra obtained are similar compared to commercial MCA's. The results obtained show that the MCA in MCU is efficient for nuclear spectrometry, in addition to being very economical and low power consumption.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of Broadcast Engineering
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• v.10 no.4 s.29
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• pp.528-539
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• 2005

The H.264 has been adopted as the video codec for various multimedia services such as DMB and next-generation DVD because of its superior coding performance. However, the reference codec of the standard, the joint model (JM) contains quite a few algorithms which are too complex to be used for the resource-constraint embedded environment. This paper introduces very low-complexity H.264 encoding algorithm which is applicable for the embedded environment. The proposed algorithm was realized by restricting some coding tools on the basis that it should not cause too severe degradation of RD-performance and adding a few early termination and bypass conditions during the motion estimation and mode decision process. In case of encoding of 7.5fps QCIF sequence with 64kbpswith the proposed algorithm, the encoder yields worse PSNRs by 0.4 dB than the standard JM, but requires only $15\%$ of computational complexity and lowers the required memory and power consumption drastically. By porting the proposed H.264 codec into the PDA with Intel PXA255 Processor, we verified the feasibility of the H.264 based MMS(Multimedia Messaging Service) on PDA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.182-192
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• 2010

This paper proposes the hardware IP design of JBIG2 encoder. In order to facilitate the next generation FAX after the standardization of JBIG2, major modules of JBIG2 encoder are designed and implemented, such as symbol extraction module, Huffman coder, MMR coder, and MQ coder. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the synthesis of VHDL code. To minimize the memory usage, 128 lines of input image are processed succesively instead of total image. The synthesized IPs are downloaded to Virtex-4 FX60 FPGA on ML410 development board. The four synthesized IPs utilize 36.7% of total slice of FPGA. Using Active-HDL tool, the generated IPs were verified showing normal operation. Compared with the software operation using microblaze cpu on ML410 board, the synthesized IPs are better in operation time. The improvement ratio of operation time between the synthesized IP and software is 17 times in case of symbol extraction IP, and 10 times in Huffman coder IP. MMR coder IP shows 6 times faster and MQ coder IP shows 2.2 times faster than software only operation. The synthesized H/W IP and S/W module cooperated to succeed in compressing the CCITT standard document.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.4
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• pp.17-22
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• 2012

Convolution filtering methods have been widely applied to various digital signal processing fields for image blurring, sharpening, edge detection, and noise reduction, etc. According to their application purpose, the filter mask size or shape and the mask value are selected in advance, and the designed filter is applied to input image for the convolution processing. In this paper, we proposed an image processing acceleration method for the convolution processing by using two-dimensional Look-up table (LUT) and overlap-region buffering technique. First, based on the fixed convolution mask value, the multiplication operation between 8 or 10 bit pixel values of the input image and the filter mask values is performed a priori, and the results memorized in LUT are referred during the convolution process. Second, based on symmetric structural characteristics of the convolution filters, inherent duplicated operation region is analysed, and the saved operation results in one step before in the predefined memory buffer is recalled and reused in current operation step. Through this buffering, unnecessary repeated filter operation on the same regions is minimized in sequential manner. As the proposed algorithms minimize the computational amount needed for the convolution operation, they work well under the operation environments utilizing embedded systems with limited computational resources or the environments of utilizing general personnel computers. A series of experiments under various situations verifies the effectiveness and usefulness of the proposed methods.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.3
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• pp.191-198
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• 2009

The FAT (File Allocation Table) compatible file system has been widely used in mobile devices and memory cards because of its data exchangeability among numerous platforms recognizing the FAT file system. By the way. modern embedded systems have tough demands for instant power failure recovery and superior performance for multimedia applications. The key issue is how to achieve the goals of superior write performance and instant booting capability while controlling compatibility issues. To achieve the goals while controlling compatibility issues. we devised a temporary meta-data journaling scheme for a FAT compatible file system. Benchmark results of the scheme implemented in a FAT compatible file system shows that it really improves write performance of the FAT file system by converting small random write for meta-data update to a large sequential write in journaling area. Also, it provides natural way to implement the instant booting capability. Nevertheless, the file system compatibility is temporarily compromised by the scheme because it stores updated meta-data in the temporary journaling area rather than to their original locations. However, the compatibility can be fully recovered at any time by journal-flushing that copies meta-data in journaling area to their original locations. Generally, the journal-flushing is done before un-mounting a memory card so that it can be used in other mobile devices which recognized FAT file system but not the temporary meta-data journaling scheme.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.4
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• pp.232-243
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• 2002

There are many methods for improving TLB (translation lookaside buffer) performance, such as increasing the number of entry in TLB, supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. So, we propose the new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub-fully associative TLBs. These two banked-TLB structures are integrated into a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also power consumption can be reduced by around 50% comparing with the fully associative TLB.