• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.254-254
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• 2011

The memories with nano-particles are very attractive because they are promising candidates for low operating voltage, long retention time and fast program/erase speed. In recent, various nano-floating gate memories with metal-oxide nanocrystals embedded in organic and inorganic layers have been reported. Because of the carrier generation in semiconductor, induced photon pulse enhanced the program/erase speed of memory device. We studied photo-induced electrical properties of these metal-oxide nanocrystal memory devices. At first, 2~10-nm-thick Sn and In metals were deposited by using thermal evaporation onto Si wafer including a channel with $n^+$ poly-Si source/drain in which the length and width are 10 ${\mu}m$ each. Then, a poly-amic-acid (PAA) was spin coated on the deposited Sn film. The PAA precursor used in this study was prepared by dissolving biphenyl-tetracarboxylic dianhydride-phenylene diamine (BPDA-PDA) commercial polyamic acid in N-methyl-2-pyrrolidon (NMP). Then the samples were cured at 400$^{\circ}C$ for 1 hour in N atmosphere after drying at 135$^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was followed by using a thermal evaporator, and then the gate electrode was defined by photolithography and etching. The electrical properties were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. Also, the optical pulse for the study on photo-induced electrical properties was applied by Xeon lamp light source and a monochromator system.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.35-40
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• 2010

NAND flash memory has been widely used than traditional HDD in PDA and other mobile devices, embedded systems, PC because of faster access speed, low power consumption, vibration resistance and other benefits. DiskSim and other HDD simulators has been developed that for find improvements for the software or hardware. But there is a few Linux-based simulators for NAND flash memory and SSD. There is necessary for Windows-based NAND flash simulator because storage devices and PC using Windows. This paper describe for development of simulator-NFSim for FTL performance analysis in NAND flash. NFSim is used to measure performance of various FTL algorithms and FTL wear-level. NAND flash memory model and FTL algorithm developed using Windows Driver Model and class for scalability. There is no need for another tools because NFSim using graph tool for data measure of FTL performance.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.9
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• pp.898-903
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• 2010

Popularity of smartphones such as Google Android phones and Apple iphones, is increasing the demand on more reliable high performance file system for flash memory. In this paper, we propose two techniques to improve the performance of YAFFS (Yet Another Flash File System), while enhancing the reliability of the system. Specifically, we first propose to manage metadata and user data separately on segregated blocks and indexing information piggy-back technique for reducing mount time and also enhancing performance. Second, we tailor the wear-leveling to the segregated metadata and user data blocks. Performance evaluation results based on real hardware system with 1GB NAND flash memory show that the YAFFS with our proposed techniques realized outperforms the original YAFFS by six times in terms of mount speed and five times in terms of benchmark performance, while reducing the average erase count of blocks by 14%.

• The KIPS Transactions:PartA
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• v.15A no.6
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• pp.335-344
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• 2008

We propose an adaptive garbage collection technique for hybrid flash memory which has both SLC and MLC. Since SLC area is fast and MLC area has low cost, the proposed scheme utilizes the SLC area as log buffer and the MLC area as data block. Considering the high write cost of MLC flash, the garbage collection for the SLC log buffer moves a page into the MLC data block only when the page is cold or the page migration invokes a small cost. The other pages are moved within the SLC log buffer. Also it adjusts the parameter values which determine the operation of garbage collection adaptively considering I/O pattern. From the experiments, we can know that the proposed scheme provides better performance compared with the previous flash management schemes for the hybrid flash and finds the parameter values of garbage collection close to the optimal values.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.5
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• pp.129-134
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• 2024

Radar signal processing boards have been widely used in embedded systems with architectures including DSPs and FPGAs. There is high-speed real-time communication between DSP and FPGA, high-speed real-time communication between DSP and DSP, and high-speed communication between FPGA and external radar components. This paper describes general communication interfaces such as memory and External Memory Interface (EMIF), HyperLink between DSP, SRIO (Serial Rapidio) between FPGA and DSP, PCIe (PCI Express), RS422 communication with FPGA and external components for DSP to boot, and describes how to implement high communication performance using these interfaces. In particular, high-speed communication between DSP and FPGA is explained by analyzing speed and performance. And previously, it describes how to receive a lot of information at high speed via RS422 communication, from the method of parallel processing individual signals through multiple signals in order to control the external radar components and receive information. The new method improves the communication speed and performance of the radar signal processing board.

• Journal of Broadcast Engineering
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• v.25 no.2
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• pp.200-207
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• 2020

Recently, deep neural networks such as CNN are showing excellent performance in various fields such as image classification, object recognition, visual quality enhancement, etc. However, as the model size and computational complexity of deep learning models for most applications increases, it is hard to apply neural networks to IoT and mobile environments. Therefore, neural network compression algorithms for reducing the model size while keeping the performance have been being studied. In this paper, we apply few compression methods to CNN models and evaluate their performances in the embedded environment. For evaluate the performance, the classification performance and inference time of the original CNN models and the compressed CNN models on the image inputted by the camera are evaluated in the embedded board equipped with QCS605, which is a customized AI chip. In this paper, a few CNN models of MobileNetV2, ResNet50, and VGG-16 are compressed by applying the methods of pruning and matrix decomposition. The experimental results show that the compressed models give not only the model size reduction of 1.3~11.2 times at a classification performance loss of less than 2% compared to the original model, but also the inference time reduction of 1.2~2.21 times, and the memory reduction of 1.2~3.8 times in the embedded board.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.4
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• pp.315-324
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• 2005

VOD(video on demand) is a video service by users' order, that is, a video service on demand. That means the users can select and watch the video content that has been saved on sewer, out of broadcasting in the usual process like TV. At present the client of VOD system bases on PC. As the PC-based client uses the software MPEG decoder, the main processor specification has an effect on the capacity. Also people, who don't know how to use their PC, cannot be provided the VOD service. The purpose of this paper is to show the process of the development the VOD client system Into the embedded type with hardware MPEG-4 decoder. The main processor is the SC1200 of x86 Family in National Semiconductor with a built-in video processor and the memory is 128Mbyte SDRAM. Also, in order that the VOD service can be provided using the Internet, the Ethernet controller is included. As the hardware MPEG-4 decoder is used in the embedded VOD client system, which is developed, it can make the low capacity of the main processor. Therefore it is able to be developed as a low-price system. The embedded VOD client system is easy for anyone to control easily with the remote control and can be played through TV.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.7-17
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• 2010

In this paper, an innovative low-power SRAM based on 4-transistor latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. Moreover, the design reduces the leakage current in the memory cells. The proposed SRAM has been demonstrated through 16-kbit test chip fabricated in a 0.18-${\mu}m$ CMOS process. It shows 17.5 ns access at 1.8-V supply while consuming dynamic power of $87.6\;{\mu}W/MHz$ (for read cycle) and $70.2\;{\mu}W/MHz$ (for write cycle). Compared with those of the conventional 6-transistor SRAM, it exhibits the power reduction of 30 % (read) and 42 % (write) respectively. Silicon measurement also confirms that the proposed SRAM achieves nearly 64 % reduction in the total standby power dissipation. This novel SRAM might be effective in realizing low-power embedded memory in future mobile applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.156-157
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• 2012

단일 셀에서 비휘발성 및 고속의 휘발성 메모리를 모두 구동할 수 있는 다기능 메모리는 모바일 기기 및 embedded 장치의 폭발적인 성장에 있어 그 중요성이 커지고 있다. 따라서 최근 이러한 fusion기술을 응용한 unified RAM (URAM)과 같은 다기능 메모리의 연구가 주목 받고 있다. 이러한 다목적 메모리는 주로 silicon on insulator (SOI)기반의 1T-DRAM과 SONOS기술 기반의 비휘발성 메모리의 조합으로 이루어진다. 하지만 이런 다기능 메모리는 주로 단결정기반의 SOI wafer 위에서 구현되기 때문에 값이 비싸고 사용범위도 제한되어 있다. 따라서 이러한 다기능메모리를 다결정 실리콘을 이용하여 제작한다면 기판에 자유롭게 메모리 적용이 가능하고 추후 3차원 적층형 소자의 구현도 가능하기 때문에 다결정실리콘 기반의 메모리 구현은 필수적이라고 할 수 있겠다. 본 연구에서는 다결정실리콘을 이용한 channel recessed구조의 다기능메모리를 제작하였으며 각 1T-DRAM 및 NVM동작에 따른 memory 특성을 살펴보았다. 실험에 사용된 기판은 상부 비정질실리콘 100 nm, 매몰산화층 200 nm의 SOI구조의 기판을 이용하였으며 고상결정화 방법을 이용하여 $600^{\circ}C$ 24시간 열처리를 통해 결정화 시켰다. N+ poly Si을 이용하여 source/drain을 제작하였으며 RIE시스템을 이용하여 recessed channel을 형성하였다. 상부 ONO게이트 절연막은 rf sputter를 이용하여 각각 5/10/5 nm 증착하였다. $950^{\circ}C$ N2/O2 분위기에서 30초간 급속열처리를 진행하여 source/drain을 활성화 하였다. 계면상태 개선을 위해 $450^{\circ}C$ 2% H2/N2 분위기에서 30분간 열처리를 진행하였다. 제작된 Poly Si MFM에서 2.3V, 350mV/dec의 문턱전압과 subthreshold swing을 확인할 수 있었다. Nonvolatile memory mode는 FN tunneling, high-speed 1T-DRAM mode에서는 impact ionization을 이용하여 쓰기/소거 작업을 실시하였다. NVM 모드의 경우 약 2V의 memory window를 확보할 수 있었으며 $85^{\circ}C$에서의 retention 측정시에도 10년 후 약 0.9V의 memory window를 확보할 수 있었다. 1T-DRAM 모드의 경우에는 약 $30{\mu}s$의 retention과 $5{\mu}A$의 sensing margin을 확보할 수 있었다. 차후 engineered tunnel barrier기술이나 엑시머레이저를 이용한 결정화 방법을 적용한다면 device의 특성향상을 기대할 수 있을 것이다. 본 논문에서는 다결정실리콘을 이용한 다기능메모리를 제작 및 메모리 특성을 평가하였다. 제작된 소자의 단일 셀 내에서 NVM동작과 1T-DRAM동작이 모두 가능한 것을 확인할 수 있었다. 다결정실리콘의 특성상 단결정 SOI기반의 다기능 메모리에 비해 낮은 특성을 보여주었으나 이는 결정화방법, high-k절연막 적용 및 engineered tunnel barrier를 적용함으로써 해결 가능하다고 생각된다. 또한 sputter를 이용하여 저온증착된 O/N/O layer에서의 P/E특성을 확인함으로써 glass위에서의 MFM구현의 가능성도 확인할 수 있었으며, 차후 system on panel (SOP)적용도 가능할 것이라고 생각된다.

• Journal of KIISE:Databases
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• v.35 no.1
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• pp.67-83
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• 2008

In order to realize ubiquitous computing, it is essential to efficiently use the resources and the computing power of mobile devices. Among others, memory efficiency, energy efficiency, and processing efficiency are required in executing the softwares embedded in mobile devices. In this paper, query processing over XML data in a mobile device where resources are limited is addressed. In a device with limited amount of memory, the techniques of XML. stream query processing need to be employed to process queries over a large volume of XML data Recently, a technique Galled XFrag was proposed whereby XML data is fragmented with the hole-filler model and streamed in fragments for processing. With XFrag, query processing is possible in the mobile device with limited memory without reconstructing the XML data out of its fragment stream. With the hole-filler model, however, memory efficiency is not high because the additional information on holes and fillers needs to be stored. In this paper, we propose a new technique called XFLab whereby XML data is fragmented with the XML labeling scheme which is for representing the structural relationship in XML data, and streamed in fragments for processing. Through implementation and experiments, XML showed that our XFLab outperformed XFrag both in memory usage and processing time.