• Journal of KIISE
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• v.42 no.4
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• pp.434-441
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• 2015

Next generation memory technologies, which we denote as 'new memory', have both non-volatile and byte addressable properties. These characteristics are expected to bring changes to the conventional computer system structure. In this paper, we propose a fast boot technique for hybrid main memory architectures that have both new memory and DRAM. The key technique used for fast booting is write-tracking. Write-tracking is used to detect and manage modified data detection and involves setting the kernel region to read-only. This setting is used to trigger intentional faults upon modification requests. As the fault handler can detect the faulting address, write-tracking makes use of the address to manage the modified data. In particular, in our case, we make use of the MMU (Memory Management Unit) translation table. When a write occurs to the boot completed state, write-tracking preserves the original state of the modified address of the kernel region to a particular location, and execution continues. Upon booting, the fast booting process restores the preserved data to the original kernel region allowing rapid system boot-up. We develop the fast booting technique in an actual embedded board equipped with new memory. The boot time is reduced to less than half a second compared to around 15 seconds that is required for the original system.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.3
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• pp.171-180
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• 2009

Slowly, but surely, we are seeing the emergence of a variety of embedded systems that are employing Storage Class RAM (SCRAM) such as FeRAM, MRAM and PRAM, SCRAM not only has DRAM-characteristic, that is, random byte-unit access capability, but also Disk-characteristic, that is, non-volatility. In this paper, we propose a new software architecture that allows SCRAM to be used both for main memory and for secondary storage simultaneously- The proposed software architecture has two core modules, one is a SCRAM driver and the other is a SCRAM manager. The SCRAM driver takes care of SCRAM directly and exports low level interfaces required for upper layer software modules including traditional file systems, buddy systems and our SCRAM manager. The SCRAM manager treats file objects and memory objects as a single object and deals with them in a unified way so that they can be interchanged without copy overheads. Experiments conducted on real embedded board with FeRAM have shown that the SCRAM driver indeed supports both the traditional F AT file system and buddy system seamlessly. The results also have revealed that the SCRAM manager makes effective use of both characteristics of SCRAM and performs an order of magnitude better than the traditional file system and buddy system.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.11-20
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• 1999

The data transfer width between the mocroprocessor and the memory comes to a critical part that limits system performance since the data transfer width has been as it was while the performance of a microprocessor is getting higher due to its continuous development in speed. And it is important that the memory should be in small size for the reduction of embedded microprocessor's price which is integrated on a single chip with the memory and IO circuit. In this paper, a mocroprocessor tentatively named as Extendable Instruction Set Computer(EISC) is proposed as the high code density 32 bit mocroprocessor architecture. The 32 bit EISC has 16 general purpose registers and 16 bit fixed length instruction which has the short length offset and small immediate operand. By using and extend register and extend flag, the offset and immediate operand could be extended. The proposed 32 bit EISC is implemented with an FPGA and all of its functions have been tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit EISC shows 140-220% and 120-140% higher code density than RISC and CISC respectively, which is much higher than any other traditional architectures. As a consequence, the EISC is suitable for the next generation computer architecture since it requires less data transfer width compared to any other ones. And its lower memory requirement will embedded microprocessor more useful.

• Journal of Adhesion and Interface
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• v.9 no.3
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• pp.20-26
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• 2008

It is well know that the structure of shape memory alloy (SMA) can change from martensite austenite by either temperature or stress. Due to their inherent shape recovery properties, SMA fiber can be used such as for stress or cure-monitoring sensor or actuator, during applied stress or temperature. Incomplete superelasticity was observed as the stress hysteresis at stress-strain curve under cyclic loading test and temperature change. Superelasticity behavior was observed for the single-SMA fiber/epoxy composites under cyclic mechanical loading at stress-strain curve. SMA fiber or epoxy embedded SMA fiber composite exhibited the decreased interfacial properties due to the cyclic loading and thus reduced shape memory performance. Rigid epoxy and the changed interfacial adhesion between SMA fiber and epoxy by the surface treatment on SMA fiber exhibited similar incomplete superelastic trend. Epoxy embedded single SMA fiber exhibited the incomplete recovery during cure process by remaining residual heat and thus occurring residual stress in single SMA fiber/epoxy composite.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.83-93
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• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.5
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• pp.101-106
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• 2020

Since computer became available, much effort has been made to achieve information security. Even though memory protection defense mechanisms were studied the most among of them, the problems of existing memory protection defense mechanisms were found due to improved performance of computer and new defense mechanisms were needed due to the advent of the side-channel attacks. In this paper, we propose JMP+RAND that embedding random values of 5 to 8 bytes per page to defend against memory sharing based side-channel attacks and bridging the gap of existing memory protection defense mechanism. Unlike the defense mechanism of the existing side-channel attacks, JMP+RAND uses static binary rewriting and continuous jmp instruction and random values to defend against the side-channel attacks in advance. We numerically calculated the time it takes for a memory sharing-based side-channel attack to binary adopted JMP+RAND technique and verified that the attacks are impossible in a realistic time. Modern architectures have very low overhead for JMP+RAND because of the very fast and accurate branching of jmp instruction using branch prediction. Since random value can be embedded only in specific programs using JMP+RAND, it is expected to be highly efficient when used with memory deduplication technique, especially in a cloud computing environment.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2588-2593
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• 2003

Any system has the possibility of an error occurrence. Even if trivial errors were occurred, the original system would be fatally affected by the occurring errors. Accordingly, the error detection must be demanded. In this paper, we developed a real-time error detection system would be able to apply to an electronic Jacquard system. A Jacquard is a machine, which controls warps while weaving textiles, for manufacturing patterned cloth. There are two types of mechanical and electronic Jacquard. An electronic Jacquard is better than a mechanical Jacquard in view of the productivity and realizability for weaving various cloths. Recent weaving industry is growing up increasingly due to the electronic Jacquard. But, the problem of wrong weaving from error data exists in the electronic Jacquard. In this research, a real-time error detection system for an electronic Jacquard is developed for detecting errors in an electronic Jacquard in real-time. The real-time system is constructed using PC-based embedded system architecture. The system detects the occurring errors in real-time by storing 1344 data transferred in serial from an electronic Jacquard into memory, and then by comparing synchronously 1344 data stored into memory with 1344 data in a design file before the next data would be transferred to the Jacquard for weaving. The information of detected errors are monitored to the screen and stored into a file in real-time as the outputs of the system. In this research, we solve the problem of wrong weaving through checking the weaving data and detecting the occurred errors of an electronic Jacquard in real-time.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.85-94
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• 2005

It has been reported and verified in many design experiences that a judicious utilization of the page and burst access modes supported by DRAMs contributes a great reduction in not only the DRAM access latency but also DRAM's energy consumption. Recently, researchers showed that a careful arrangement of data variables in memory directly leads to a maximum utilization of the page and burst access modes for the variable accesses, but unfortunately, found that the problems are not tractable, consequently, resorting to simple (e.g., greedy) heuristic solutions to the problems. In this parer, to improve the quality of existing solutions, we propose 0-1 ILP-based techniques which produce optimal or near-optimal solution depending on the formulation parameters. It is shown that the proposed techniques use on average 32.2%, l5.1% and 3.5% more page accesses, and 84.0%, 113.5% and 10.1% more burst accesses compared to OFU (the order of first use) and the technique in [l, 2] and the technique in [3], respectively.

• KIISE Transactions on Computing Practices
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• v.21 no.12
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• pp.792-797
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• 2015

Effective profiling diagnoses the failure of the system and informs risk. If a failure in the target system occurs, it is impossible to diagnose more than one of the exiting tools. In this respect, monitoring of the system based on virtualization is useful. We present in this paper a monitoring framework that uses the characteristics of hardware virtualization to prevent side-effects from a target guest, and uses dynamic binary instrumentation with instruction-level trapping based on hardware virtualization to achieve efficiency and flexibility. We also present examples of some applications that use this framework. The framework provides tracing of guest kernel function, memory dump, and debugging that uses GDB stub with GDB remote protocol. The experimental evaluation of our prototype shows that the monitoring framework incurs at most 2% write memory performance overhead for end users.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.1076-1087
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• 2010

Together with a new advent of embedded processor developed to support specific application area and it evolution, a new research of software development to support the embedded processor and its commercial challenge has been revitalized. Retargetability is typically achieved by providing target machine information, ADL, as input. The ADLs are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, assembler, profiler, and debugger. The EXPRESSION ADL follows a mixed level approach-it can capture both the structure and behavior supporting a natural specification of the programmable architectures consisting of processor cores, coprocessors, and memories. And it was originally designed to capture processor/memory architectures and generate software toolkit to enable compiler-in-the-loop exploration of SoC architecture. In this paper, we designed the class-based ADL based on the EXPRESSION ADL to promote the write-ability, extensibility and verified the validation of grammar. For this works, we defined 6 core classes and generated the EXPRESSION's compiler and simulator through the MIPS R4000 description.