• 대한임베디드공학회논문지
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• 제6권6호
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• pp.345-359
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• 2011

In high performance embedded systems, the use of multiple on-chip memories is an essential architectural feature for exploiting inherent parallelism in multimedia applications. This feature allows multiple data accesses to be executed in parallel. However, it remains difficult to effectively exploit of multiple on-chip memories. The successful use of this architecture strongly depends on how to efficiently detect and exploit memory parallelism in target applications. In this paper, we propose a technique based on a linear array access descriptor [1], which is generated from profiled data, to detect and exploit memory parallelism. The proposed technique tackles an array reorganization problem to maximize memory parallelism in multimedia applications. We present preliminary experiments applying the proposed technique onto a representative coarse grained reconfigurable array processor (CGRA) with multimedia kernel codes. Our experimental results demonstrate that our technique optimizes data placement by putting independent data on separate storage. The results exhibit 9.8% higher performance on average compared to the existing method.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.103-111
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• 2019

The IoT-driven large-scaled systems consist of connected things with on-chip executable embedded software. These light-weighted embedded things have limited hardware space, especially small size of on-chip flash memory. In addition, on-chip embedded software in flash memory is not easy to update in runtime to equip with latest services in IoT-driven applications. It is becoming important to develop light-weighted IoT devices with various software in the limited on-chip flash memory. The remote instruction execution in cloud via IoT connectivity enables to provide high performance software execution with unlimited software instruction in cloud and low-power streaming of instruction execution in IoT edge devices. In this paper, we propose a Cloud-IoT asymmetric structure for providing high performance instruction execution in cloud, still low power code executable thing in light-weighted IoT edge environment using remote instruction execution. We propose a simulated approach to determine efficient partitioning of software runtime in cloud and IoT edge. We evaluated the instruction cloudification using remote instruction by determining the execution time by the proposed structure. The cloud-connected instruction set simulator is newly introduced to emulate the behavior of the processor. Experimental results of the cloud-IoT connected software execution using remote instruction showed the feasibility of cloudification of on-chip code flash memory. The simulation environment for cloud-connected code execution successfully emulates architectural operations of on-chip flash memory in cloud so that the various software services in IoT can be accelerated and performed in low-power by cloudification of remote instruction execution. The execution time of the program is reduced by 50% and the memory space is reduced by 24% when the cloud-connected code execution is used.

• ETRI Journal
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• 제35권5호
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• 대한임베디드공학회논문지
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• 제2권3호
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• pp.184-193
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• 2007

Flash memory adoption in the mobile devices is increasing or vanous multimedia services such as audio, videos, and games. Although the traditional research issues such as out-place update, garbage collection, and wear-leveling are important, the performance, memory usage, and fast mount issues of flash memory file system are becoming much more important than ever because flash memory capacity is rapidly increasing. In this paper, we address the problems of the existing log-based flash memory file systems analytically and propose an efficient log-based file system, which produces higher performance, less memory usage and mount time than the existing log-based file systems. Our ideas are applied to a well-known log-based flash memory file system (YAFFS2) and the performance tests are conducted by comparing our prototype with YAFFS2. The experimental results show that our prototype achieves higher performance, less system memory usage, and faster mounting than YAFFS2, which is better than JFFS2.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 B
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• pp.672-674
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• 1998

Java virtual machine has the garbage collector that automate memory management. Mark-compact algorithm is one of the garbage collection algorithm that operating in 2 phases, marking and sweeping. One is Marking is marking live objects reachable from root object set. Sweeping is sweeping unmarked object from memory(return to free memory pool). This algorithm is easy to implement but cause a memory fragmentation. So compacting memory, before memory defragmentation become serious. When compacting memory, all other processes are suspended. It is critical for embedded system that must guarantee real-time processing. This paper introduce enhanced mark-compact garbage collection algorithm. Grouping the objects by their size that minimize memory fragmentation. Then apply smart algorithm to the grouped objects when allocating objects and compacting memory.

• 한국멀티미디어학회논문지
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• 제19권7호
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• pp.1179-1187
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• 2016

Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.

• 전자공학회논문지CI
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• 제45권3호
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• pp.75-85
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• 2008

임베디드 시스템에서 데이터베이스의 사용이 증가하고 있으며 이의 임베디드 시스템의 저장 장치로 낸드 플래시 메모리가 널리 사용되고 있다. 기존 데이터베이스 시스템의 질의 처리기의 최적화기는 저장 시스템을 디스크로 가정하고 설계되어 있다. 플래시 메모리는 디스크와는 달리 덮어 쓰기 연산을 하기 위해서는 기존 블록을 소거한 후 쓰기 연산을 해야하는 부담이 있다. 그러므로 기존 디스크 기반의 질의 최적화기는 임베디드 시스템에 적합하지 않다. 특히 임베디드 시스템은 전력 소모량을 최소화해야 하나 플래시에서의 빈번한 쓰기 연산은 추가적인 소거 연산으로 인한 전력 소비를 증진시킨다. 본 논문은 임베디드 데이터베이스에서 전력 기반 비용 모델을 새롭게 제시하고, 디스크 기반 비용 모델과 비교하여 제시한 비용 모델과의 차이를 보인다.

• 전자공학회논문지
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• 제50권11호
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• pp.117-123
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• 2013

비터비 디코더(Viterbi decoder)용 임베디드 SRAM은 범용(General purpose) CPU에 쓰이는 SRAM과 달리 읽기, 쓰기 동작이 비터비 복호 알고리즘에 따라 일정한 액세스 패턴을 갖고 동작한다. 이 연구를 통하여 제안된 임베디드 SRAM의 구조는 이러한 메모리 동작의 패턴에 최적화되어 워드라인과 비트라인에서 발생하는 불필요한 전력소모를 제거함으로써 쓰기 동작의 소모 전력을 크게 줄일 수 있다. 65nm CMOS 공정으로 설계된 비터비 디코더는 본 논문에서 제안된 SRAM 구조를 이용하여 기존의 임베디드 SRAM 대비 8.92%만큼 면적증가로 30.84% 소모 전력 감소를 이룩할 수 있었다.

• 대한임베디드공학회논문지
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• 제12권3호
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• pp.159-167
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• 2017

Software safety is a key issue in embedded system of automotive and aviation industries. Various software testing approaches have been proposed to achieve software safety like ISO26262 Part 6 in automotive environment. In spite of one of the classic and basic approaches, stack memory is hard to estimating exactly because of uncertainty of target code generated by compiler and complex nested interrupt. In this paper, we propose an approach of analyzing the maximum stack usage statically from target binary code rather than the source code that also allows nested interrupts for determining the exact stack memory size. In our approach, determining maximum stack usage is divided into three steps: data extraction from ELF file, construction of call graph, and consideration of nested interrupt configurations for determining required stack size from the ISR (Interrupt Service Routine). Experimental results of the estimation of the maximum stack usage shows proposed approach is helpful for optimizing stack memory size and checking the stability of the program in the embedded system that especially supports nested interrupts.

• 대한임베디드공학회논문지
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• 제13권5호
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• pp.261-268
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• 2018

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.