• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.40-47
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• 2007

For image processing hardware, including a face detecting engine, efficient constitution of external and internal memories is a consequential point because huge memory is required to store various signal processing filters and incoming images. In this paper, we modified a face detect algerian of a general filter method for efficient hardware design. In the hardware, several memory design techniques are presented for efficient handling of image data : re-accessing avoidance with minimized internal memory usage, residing frequently accessed memory and sequence memory accessing. The hardware which can process 25 frame image data per one second with 40KB internal memory was verified by using ARM(S3C2440A) and Virtex4 FPGA and it is being fabricated as a ASIC chip using Samsung CMOS 0.18um technology.

• Proceedings of the KSR Conference
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• 2011.10a
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• pp.188-194
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• 2011

The purpose of this paper is to explain the implementation method in order to enhance stability and reliability of embedded system. In this research, Texas Instrument (TI)'s TMS570 MCU(Micro Controller Unit) is used to satisfy the standard of stability that is IEC 61508. IEC 61508 suggest SIL(Safety Integrity Level) from 1 to 4 and TMS570 is satisfied SIL3. Also, TMS570 can provide several stability functions can be used in realtime system. To use such functions, this paper suggest the solution about the defect that can be used in realtime system. In basic way TMR(Triple Modular Redundancy) suggested in addition to explain about the way to improve safety and reliability. Also this paper will suggest the method that reinforce the stability of calculation by using multiplex voter and memory.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.3
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• pp.194-201
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• 2007

As the performance of the mobile terminal becomes higher, the power consumption gradually increases. As a result, power management is one of the most important issues in mobile system with battery. In this paper, we describe an DPM(Dynamic Power Management) using DVS(Dynamic Power Management) as a power management mechanism in Qplus operating system. DVS generally considers a specific device such as CPU, whereas we consider the relations with other hardware components as well as each component. We specially focus on the relation between CPU, memory and LCD devices. We also designs a kernel monitor to collect information to decide the policy for power management. According to the experimental results, the proposed method enables to save much power.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.6
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• pp.369-375
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• 2017

In this paper, we present a self-adaptive software platform that enables an IoT gateway to perform autonomous operation considering IoT devices connected each other in resource-constrained environments. Based on the oneM2M device software platform publicly available, we have designed an additional part, called SAS (self-adaptive software) consisting of MAM (memory-aware module), NAM (network-aware module), BAM (battery-aware module), DAM (data-aware module), and DH (decision handler). A prototype system is implemented to show the feasibility of the proposed self-adaptive software architecture. Our proposed system demonstrates that it can adaptively adjust the operation of gateway and connected devices to their resource conditions under the desired service scenarios.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.141-151
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• 1994

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.624-629
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• 2016

The influence of electron and hole (EH) distribution on two-transistor (2T) silicon-oxide-nitride-oxide-silicon (SONOS) embedded nonvolatile memory (eNVM) is investigated in terms of reliability. As PE (program/erase) cycles are repeated, it is observed that the electron distribution in the nitride layer becomes wider. It leads to the EH distribution mismatch, which degrades the reliability of 2T SONOS eNVM.

• IEMEK Journal of Embedded Systems and Applications
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• v.1 no.1
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• pp.14-19
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• 2006

Integrated development environment (IDE) plays an important role in reducing the developm ent time, thereby improving software development productivity. In recent years, ubiquitous sensor networks (USNs) have become increasingly popular. However their application software is developed mostly using command-line-based tools. Such a development process is not only likely to be error-prone but also inconvenient to debug errors. This paper describes a novel IDE for USN application developers called Nano Esto that provides a single, consistent, and integrated environment for building and executing USN applications. The Nano Esto helps the developers edit and cross-compile source code and download the executable image to the program memory of sensor nodes with just a few button clicks. It also provides support for configuring an application-specific kernel, simulating a wireless sensor network, and estimating power consumption in each sensor node. Currently, Nano Esto runs on Linux as well as on Windows with the same look and feel.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.173-179
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• 2012

In this paper, we propose an efficient architecture for 2D IWT using an existing 1D IWT. Lifting based IWT is the architecture of which a multiplier is replaced by adders and shift registers. The structure is relatively simple and modular. The proposed architecture to process an image size with 256x256 pixels consists of 16 adders, 8 shift registers, and some memories. By processing two rows at the same time, 2D sub-band coefficients can be calculated immediately after 1D sub-band coefficients have been processed. The architecture is designed so that each image can be inputted consecutively. The number of adders and shift registers is increased by twice comparing the existing architecture, but the memory size and the execution time are decreased by half. The proposed architecture is implemented using Verilog-HDL and simulated using iSim. It is synthesized and demonstrated at ISE for xc5vlx330 in RPS3K board.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.1
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• pp.1-8
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• 2007

In this paper, we developed a file system architecture for portable multimedia devices. To enhance user convenience, the information about the stored files should be easily retrieved and organized. We defined NMD (Networked MetaData), which can organize the files in networked fashion by attaching user-defined attributes and relation between files. The NMD is stored in flash memory to utilize its nonvolatile property and low-power consumption, while multimedia files are stored in hard disk, an inexpensive mass storage. The experimental implementation showed that this architecture was able to save about 10% power compared to the hard disk NMD-store.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.2
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• pp.201-206
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• 2004

This study attempted to develop a speech recognition module applied to a wheelchair for the physically handicapped. In the proposed speech recognition module, TMS320C32 was used as a main processor and Mel-Cepstrum 12 Order was applied to the pro-processor step to increase the recognition rate in a noisy environment. DTW (Dynamic Time Warping) was used and proven to be excellent output for the speaker-dependent recognition part. In order to utilize this algorithm more effectively, the reference data was compressed to 1/12 using vector quantization so as to decrease memory. In this paper, the necessary diverse technology (End-point detection, DMA processing, etc.) was managed so as to utilize the speech recognition system in real time