• Journal of the Korea Society for Simulation
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• v.25 no.1
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• pp.35-43
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• 2016

Increasing the proportion of an embedded system in automotive industry, test methods for evaluation and fault detection of the embedded system have been researched. HILS is a test method that is used in the development and test of complex real-time embedded systems. In this study, we defined the HILS method of the ECU, one of the embedded systems used in automobiles. Our method is to create a test model that can provide a virtual vehicle environment to the ECU on the basis of the actual vehicle data. The test model has reference information that can transmit the sensor signal and CAN Message into the ECU from HILS tester. In this study, the HILS can detect faults of the target ECU.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.6
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• pp.369-377
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• 2016

Recently, many changes have been made to people's life patterns as the technological advances in the ICT industry. The fusion of smart phones and various IT technologies has brought people convenience and welfare. A typical example of such fusion is the smart home. However, the existing smart home systems are difficult to be changed or extended. So we design a new smart home system with extensibility that can easily adopt legacy appliances and be scaled up. Among a variety of smart home features, this paper deals with IoT Devices that are responsible for controlling power or transmitting and receiving sensing values, IoT Gateway that connects users and consumer electronics via Internet, and Smart Home Manager that monitors and controls these components in the proposed smart home system.

• Journal of the Korea Safety Management & Science
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• v.14 no.4
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• pp.219-227
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• 2012

The trend is going to obtain the accurate and fast information to the development of information technology and electronic technology as an important part of corporate management. Press equipment to produce products that target is small and medium businesses. Became so economical real-time production information system(R-PIS) model has been implemented. R-PIS configure the embedded hardware and PC application software. This system is easy maintenance and upgrade that general-purpose PC and a modular hardware devices. Consists of modules such as wireless communication, LCD, Key-pad, memory control, and sensor signal. R-PIS is efficient materials and product management to maximize the productivity of the enterprise.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.779-781
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• 2007

Nowadays, as the increasing functionality and scales of embedded systems, system design grows more complex than before. So verification and simulation of systems become an important facet in hardware-software co-design issues. But it is almost impossible to simulate an embedded system without real hardware implementation or environment communication, especially for control-dominated reactive systems. Therefore, in this paper, we will introduce a GUI environment module generator for integrated Esterel\C++ simulation. By generating the GUI modeling environment, we can simulate and verify the whole embedded system conveniently.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.414-418
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• 2016

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.141-146
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• 2017

In this paper, a gradient magnitude hardware architecture based on hardware folding design method is proposed for low power image feature extraction. For the hardware complexity reduction, the projection vector chracteristic of gradient magnitude is applied. The proposed hardware architecture can be implemented with the small degradation of the gradient magnitude data quality. The FPGA implementation result shows the 41% of logic elements and 62% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v16.0 environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.22-30
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• 2011

Recently, the rising demand for intelligent video surveillance system leads to high-performance face recognition systems. The solution for low-resolution images acquired by a long-distance camera is required to overcome the distance limits of the existing face recognition systems. For that reason, this paper proposes a hardware design of an image resolution enhancement algorithm for real-time intelligent video surveillance systems. The algorithm is synthesizing a high-resolution face image from an input low-resolution image, with the help of a large collection of other high-resolution face images, called training set. When we checked the performance of the algorithm at 32bit RISC micro-processor, the entire operation took about 25 sec, which is inappropriate for real-time target applications. Based on the result, we implemented the hardware module and verified it using Xilinx Virtex-4 and ARM9-based embedded processor(S3C2440A). The designed hardware can complete the whole operation within 33 msec, so it can deal with 30 frames per second. We expect that the proposed hardware could be one of the solutions not only for real-time processing at the embedded environment, but also for an easy integration with existing face recognition system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3C
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• pp.398-407
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• 2004

In this paper, a blind watermarking method which is suitable to the video compression using 2-D discrete wavelet transform was proposed and implemented into the hardware using VHDL(VHSIC Hardware Description Language). The goal of the proposed watermarking algorithm is the authentication about the manipulation of the watermark embedded image and the detection of the error positions. Considering the compressed video image, the proposed watermarking scheme is unrelated to the quantization and is able to concurrently embed or extract the watermark. We experimentally verified that the lowest frequency subband(LL4) is not sensitive to the change in the spatial domain, so LL4 subband was selected for the mark space. And the combination of the bitplanes which has the properties of both the minimum degradation of the image and the robustness was chosen as the embedded Point in the mark space in LL4 subband. Since we know the watermark embedded positions and the watermark is embedded by not varying the value but changing the value, the watermark can be extracted without the original image. Also, for the security when exposing the watermark embedded position, we embed the encrypted watermark by the block cipher. The proposed watermark algorithm shows the robustness against the general image manipulation and is easily transplanted into the image or video compressor with the minimal changing in the structure. The designed hardware has 4037 LABs(24％) and 85 ESBs(3％) in APEX20KC EP20K400CF672C7 FPGA of Altera and stably operates in 82MHz clock frequency.

• 전기의세계
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• v.41 no.5
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• pp.14-19
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• 1992

Microprocessor의 성능은 향상되는 반면 관련 hardware의 가격은 계속 하락하고 있다. 따라서 자동화 기기와 같은 특수기기내에서 microprocessor관련 hareware의 비용이 전체기기의 가격에서 차지하는 비중이 점차로 줄어들고 있고 이와 같은 기기류에 32bit microporcessor와 같은 고성능의 hardware를 장착하는 경우가 늘고 있다. 그러나 이에 걸맞는 software의 제작은 결코 쉬운 일이 아니다. 이와같은 고성능의 기기에 필요한 적절한 software의 제작 및 유지보수를 위해서는 반드시 적절한 개발환경이 필수적이라고 할 수 있다.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.691-698
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• 2006

TCP/IP Offload Engine (TOE) is a technology that processes TCP/IP on a network adapter instead of a host CPU to reduce protocol processing overhead from the host CPU. There have been some approaches to implementing TOE: software TOE based on an embedded processor; hardware TOE based on ASIC implementation; and hybrid TOE in which software and hardware functions are combined. In this paper, we designed software modules and hardware modules for a hybrid TOE on an FPGA that had two processor cores. Software modules are based on the embedded Linux. Hardware modules are for data transmission (TX) and reception (RX). One core controls the TX path and the other controls the RX path of the Linux. This TX/RX path separation mechanism can reduce task switching overheads between processes and overcome poor performance of single embedded processor. Hardware modules deal with creating headers for outgoing packets, processing headers of incoming packets, and fetching or storing data from or to the host memory by DMA. These can make it possible to improve the performance of data transmission and reception. We proved performance of the TOE with separated transmission and reception paths by performing experiments with a TOE network adapter that was equipped with the FPGA having processor cores.