• Journal of KIISE
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• v.42 no.8
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• pp.990-997
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• 2015

Panoramic image creation has been extensively studied. Existing methods use customized hardware, or apply post-processing methods to seamlessly stitch images. These result in an increase in either cost or complexity. In addition, images can only be stitched under certain conditions such as existence of characteristic points of the images. This paper proposes a low cost and easy-to-use system that produces realtime panoramic video. We use an off-the-shelf embedded platform to capture multiple images, and these are then transmitted to a server in a compressed format to be merged into a single panoramic video. Finally, we analyze the performance of the implemented system by measuring time to successfully create the panoramic image.

• Nuclear Engineering and Technology
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• v.45 no.4
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• pp.477-488
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• 2013

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.1
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• pp.34-52
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• 2019

This paper proposes an intelligent system performing an application with assistance of an Internet of Things (IoT) platform to control a traffic lights system. In our proposed systems, the traffic lights can be remotely controlled through the Internet. Based on IoT platform, the traffic conditions at different intersections of roads are collected and the traffic lights are controlled in a central manner. For the software part, the algorithm is designed based on the green wave theory to maximize the green bandwidth of arterial roads while addressing a challenging issue: the rapid changes of parameters including cycle time, splits, offset, non-fixed vehicles' velocities and traffic flow along arterial roads. The issue typically happens at some areas where the transportation system is not well organized like in Vietnam. For the hardware part, PLC S7-1200 are placed at the intersections for two purposes: to control traffic lights and to collect the parameters and transmit to a host machine at the operation center. For the communication part, the TCP/IP protocol can be done using a Profinet port embedded in the PLC. Some graphical user interface captures are also presented to illustrate the operation of our proposed system.

• Journal of Drive and Control
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• v.15 no.4
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• pp.30-38
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• 2018

Electronic control units (ECUs) are currently popular, and have evolved further towards the high-end application of autonomous vehicles in the automotive industry. Such digital technologies have also become widespread, in agriculture and construction equipment. Likewise, transmission control of high-speed tracked vehicles is based on the transmission control unit (TCU), performing complex gear change control functions, and diagnostic algorithms (a TCU's self-diagnostic and reporting capability of malfunction data through CAN communication). Since all functions of TCU are implemented by embedded-software, it is hardly possible to analyze specifications by reverse engineering. In this paper a real-time transmission simulator adaptable to TCU is presented, for analysis of diagnosis algorithm and standards. Signal simulation circuits are deliberately designed considering electrical characteristics of TCU inputs and various analysis tools, such as analog input auto scan function, and global output enable switch, are implemented in software. Test results from hardware-in-the-loop simulator verify tolerance time for each error, as well as cause of fault, error reset conditions.

• Journal of IKEEE
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• v.23 no.3
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• pp.1068-1076
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• 2019

Most of the electronics we use today have built-in microcontrollers, which are called embedded systems. In such a small environment, responsiveness is very important for the microcontroller. In this paper, the basic input/output control, timer/counter interrupt operation principle, and understanding of the microcontroller are described. Program logic is proposed to improve throughput and latency by controlling characteristics of service routine and program execution order. The hardware simulations in this paper were verified using ATmega128 and PIC16F877A from Atmel and Microchip.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.5654-5668
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• 2018

Driven by security and real-time demands of Internet of Things (IoT), the timing of fog computing and edge computing have gradually come into place. Gateways bear more nearby computing, storage, analysis and as an intelligent broker of the whole computing lifecycle in between local devices and the remote cloud. In fog computing, the edge broker requires X-aware capabilities that combines software programmability, stream processing, hardware optimization and various connectivity to deal with such as security, data abstraction, network latency, service classification and workload allocation strategy. The prosperous of Field Programmable Gate Array (FPGA) pushes the possibility of gateway capabilities further landed. In this paper, we propose a software-defined gateway (SDG) scheme for fog computing paradigm termed as Fog Computing Zero-Knowledge Gateway that strengthens data protection and resilience merits designed for industrial internet of things or highly privacy concerned hybrid cloud scenarios. It is a proxy for fog nodes and able to integrate with existing commodity gateways. The contribution is that it converts Privacy-Enhancing Technologies rules into provable statements without knowing original sensitive data and guarantees privacy rules applied to the sensitive data before being propagated while preventing potential leakage threats. Some logical functions can be offloaded to any programmable micro-controller embedded to achieve higher computing efficiency.

• Journal of IKEEE
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• v.25 no.1
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• pp.229-233
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• 2021

NPU in an embedded environment performs deep learning algorithms with few hardware resources. By using a technique that reuses data, deep learning algorithms can be efficiently computed with fewer resources. In previous studies, data is reused using a shifter in ScratchPad for data reuse. However, as the ScratchPad's bandwidth increases, the shifter also consumes a lot of resources. Therefore, we present a data reuse technique using the Buffer Round Robin method. By using the Buffer Round Robin method presented in this paper, the chip area could be reduced by about 4.7% compared to the conventional method.

• Journal of Sensor Science and Technology
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• v.30 no.1
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• pp.20-24
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• 2021

The electrocardiogram (ECG) is one of the most extensively employed signals used to diagnose and predict cardiovascular diseases (CVDs). In recent years, several deep learning (DL) models have been proposed to improve detection accuracy. Among these, deep neural networks (DNNs) are the most popular, wherein the features are extracted automatically. Despite the increment in classification accuracy, DL models require exorbitant computational resources and power. This causes the mapping of DNNs to be slow; in addition, the mapping is challenging for a wearable device. Embedded systems have constrained power and memory resources. Therefore full-precision DNNs are not easily deployable on devices. To make the neural network faster and more power-efficient, spiking neural networks (SNNs) have been introduced for fewer operations and less complex hardware resources. However, the conventional SNN has low accuracy and high computational cost. Therefore, this paper proposes a new binarized SNN which modifies the synaptic weights of SNN constraining it to be binary (+1 and -1). In the simulation results, this paper compares the DL models and SNNs and evaluates which model is optimal for ECG classification. Although there is a slight compromise in accuracy, the latter proves to be energy-efficient.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1342-1354
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• 2016

As Internet, and hardware technology are in rapid process, using rate and penetration rate of Internet of Things are increasing. Internet of Things is the physical objects with network which embedded with electronics, software, sensors, and network. Smart Home-kit to operate refrigerators, washing machines, light bulbs, and such internet of things by a smartphone has been realized. However, it is difficult to use a good quality of software based on IoT. It is because that the study related to quality evaluation of software based on IoT is deficient compared with increase amount of IoT devices. Software based on IoT includes mobility, transportability, real time accessibility and hardware characteristics. Therefore, it is necessary to have differentiated quality standards and quality model. Software quality evaluation model for IoT is proposed to satisfy these needs. Evaluation model is mapped by characteristics of IoT software based on ISO/IEC 25000's quality characteristics. Scenario based studies were applied to quality model for verification.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.73-83
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• 2007

In network intrusion prevention, attack packets are detected and filtered out based on their attack signatures. Pattern matching is extensively used to find attack signatures and the most time-consuming execution part of Network Intrusion Prevention Systems(NIPS). Pattern matching is usually accelerated by hardware and should be performed at wire speed in NIPS. However, that alone is not good enough. First, pattern matching hardware should be able to generate sufficient pattern match information including the pattern index number and the location of the match found at wire speed. Second, it should support pattern grouping to reduce unnecessary pattern matches. Third, it should always have a constant worst-case performance even if the number of patterns is increased. Finally it should be able to update patterns in a few minutes or seconds without stopping its operations, We propose a system architecture to meet the above requirement. The system architecture can process multiple pattern characters in parallel and employs a pipeline architecture to achieve high speed. Using Xilinx FPGA simulation, we show that the new system stales well to achieve a high speed oner 10Gbps and satisfies all of the above requirements.