• Journal of the Korean Institute of Intelligent Systems
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• v.21 no.5
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• pp.581-587
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• 2011

This paper presents a senior-level embedded software design course using a customized training kit. Embedded software design courses commonly entail a lot of practice hours and a semester-long project and thus requires a hardware platform on which the embedded software runs. A training kit has been designed such that both hardware system and operating system are not too complicated or heavy for undergraduate students to fully understand and to develop embedded software on their own. The course using the customized training kit gives the students hands-on experience of embedded software design and programming ranging from device drivers to user interface, thereby enabling them to have in-depth understanding of embedded software and to improve their programming skills more easily and faster than when using commercial training kits.

• Journal of Korea Multimedia Society
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• v.10 no.11
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• pp.1446-1459
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• 2007

This paper presents and analyzes a novel technique that makes it possible to improve the performance of low-end embedded systems through SoC(System-on-a-Chip) platform supporting dynamic cooperation between hardware and software modules. Traditional embedded systems with limited hardware resources have the poor capability of carrying out multi-tasking jobs including complex calculations. The proposed SoC platform, which provides dynamic cooperation between hardware and software modules, decomposes a single specific system into tasks for given system requirements. Additionally, we also propose a technique for efficient communication and synchronization between hardware and software tasks in cooperation with each other. Several experiments are conducted to illustrate the application and efficiency of the proposed SoC platform. They show that the proposed SoC platform outperforms the traditional embedded system, where only software tasks run, as the number of memory access is increased and the system become more complex.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1553-1557
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• 2004

A real-time processing system for embedded hardware genetic algorithm is suggested. In order to operate basic module of genetic algorithm in parallel, such as selection, crossover, mutation and evaluation, dual processors based architecture is implemented. The system consists of two Xscale processors and two FPGA with evolvable hardware, which enables to process genetic algorithm efficiently by distributing the computational load of hardware genetic algorithm to each processors equally. The hardware genetic algorithm runs on Linux OS and the resulted chromosome is executed on evolvable hardware in FPGA. Furthermore, the suggested architecture can be extended easily for a couple of connected processors in serial, making it accelerate to compute a real-time hardware genetic algorithm. To investigate the effect of proposed approach, performance comparisons is experimented for an typical computation of genetic algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.317-319
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• 2003

HILS(Hardware In-the Loop Simulation) is commonly used in the development and testing of embedded systems, when those systems cannot be tested easily, thoroughly, and repeated in their operational environments. HILS can be a useful tool to develop products more quickly and cost effectively and also reduces the possibility of serious defects being discovered after production. During the product development period, Design optimization and hardware/software debugging can be performed using HILS skill. This paper describes a HILS model for the STG(Steam-Turbine Generator) Simulator to prove the performance of the developed Digital Governor. It is developed using software technics which can confirm the responses of a real-time system.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.93-98
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• 2011

While the use of battery-powered embedded systems has been rapidly increasing, the current level of battery technology has not kept up with the drastic increase in power consumption by the system. In order to prolong system usage time, the battery size needs to be increased. The amounts of power consumption by embedded systems are determined by their hardware configuration and software for manipulating hardware resources. In spite of that, the hardware provides features for lowering power consumption, if those cannot be utilized efficiently by software including operating system, reduction in power consumption is not optimized. In this paper, we propose a BET(Break Even Time)-based scheduling method using task partition to reduce power consumption of multimedia applications in a mobile embedded system environment.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.474-479
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• 2014

LEON3 is a 32-bit synthesizable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7- stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the debugging tool for LEON3 based embedded systems. The debugging tool can initialize the target hardware, find out how the target hardware is configured, load application code to a specified memory space and run that application code. To provide users a debugging environment, it can set breakpoints and control the operation of LEON3 correspondingly. And function call trace is one of key functions of the debugging tool.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.481-484
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• 2007

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.48-55
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• 2010

The goal of this paper is to determine optimal hardware platform for specific applications. In order to develop an understanding of how select the optimal platform, we focus upon the real-time embedded vehicle system for processing forward image and sound. In this paper we propose to measure parameters such as instructions, execution cycle, required memory size for program and data by using ARMulator. We have measured three types of processor cores: ARM7, ARM9 and ARM10. The results of the study indicated that the proposed methods could measure the minimal requirements of hardware platform for specific applications. By defining lower limit of hardware specifications in embedded systems, we can minimize expenses with suitable system performance without implementing the system.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.5
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• pp.297-305
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• 2015

AFLS (Adaptive front lighting System) is being applied to improve safety in driving automotive at night. Safe embedded system for controlling head-lamp has to be tightly designed by considering safety requirement of hardware-dependent software, which is embedded in automotive ECU(Electronic Control Unit) hardware under severe environmental noise. In this paper, we propose an adaptive headlight controller with newly-designed symmetric angle sensor compensator, which is integrated with ECU-based adaptive front light system. The proposed system, on which additional backup hardware and emergency control algorithm are integrated, effectively detects abnormal situation and restore safe status of controlling the light-angle in AFLS operations by comparing result in symmetric angle sensor. The controlled angle value is traced into internal memory in runtime and will be continuously compared with the pre-defined lookup table (LUT) with symmetric angle value, which is used in normal operation. The watch-dog concept, which is based on using angle sensor and control-value tracer, enables quick response to restore safe light-controlling state by performing the backup sequence in emergency situation.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.151-153
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• 2006

When distributed powers are interconnected to the grid, lack of source stability may cause some events that should be measured and stored as soon as they occur. This paper presents a real-time hardware system that has been developed for quick and reliable monitoring of the distributed powers quality. The system is composed of a digital signal processor (MPC7410, Motorola) and a 16 bits A/D board (VMIVME3122, GE). To guarantee the real time operation, it is based on a real time OS (VxWorks). Hardware tests of the embedded system have been made to check the performances of the proposed system. Test signals of several events are generated by using a LabView (hardware) system. The tests show that the system complies with the desired IEEE standard for power quality monitoring.