• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.453-461
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• 2010

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of embedded RISC core and a clock-gating algorithm using ODC (Observability Don't Care) operation to improve the power consumption of the core. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC core applied the proposed architecture is improved about 29% and dynamic power of the core using Chartered $0.18{\mu}m$ technology library is reduced by 16%.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.2
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• pp.85-90
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• 2003

This paper has presented the efficient implementation of MPEG-4 simple profile video decoder, which is used as video compression standard in mobile video communication. We have used the ARM9 processor in implementing this MPEG-4 simple profile, which requires much processing power and low power implementation. At first we implemented with C-language under the PC environment with ADS(ARM Developer Suite) environment, and then we have tried to reduce a clock cycle for a power consumption optimization through conversion an assembly language for C-code partly. We have verified the processor is operated at 22.47MHz operation after optimization, but 148MHz before optimization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.273-278
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• 2012

In this contribution, we design and implement an SPI hardware interface for the microprocessor to communicate with the MMC (Multi-Media Card) in an embedded system. Proposed architecture is compatible with the APB in AMBA bus architecture. Embedding OS in an embedded system means a big burden in terms of hardware and software ending up with performance decline. In this paper, we adopt the concept of SPI communication without using OS in the embedded system and implement in a form of FPGA chip. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency, which satisfied our target speed.

• ETRI Journal
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• v.42 no.4
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• pp.480-490
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• 2020

More than 42 000 fires occur nationwide and cause over 2500 casualties every year. There is a lack of specialized equipment, and rescue operations are conducted with a minimal number of apparatuses. Through-the-wall radars (TTWRs) can improve the rescue efficiency, particularly under limited visibility due to smoke, walls, and collapsed debris. To overcome detection challenges and maintain a small-form factor, a TTWR system-on-chip (SoC) and its architecture have been proposed. Additive reception based on coherent clocks and reconfigurability can fulfill the TTWR demands. A clock-based single-chip infrared radar transceiver with embedded control logic is implemented using a 130-nm complementary metal oxide semiconductor. Clock signals drive the radar operation. Signal-to-noise ratio enhancements are achieved using the repetitive coherent clock schemes. The hand-held prototype radar that uses the TTWR SoC operates in real time, allowing seamless data capture, processing, and display of the target information. The prototype is tested under various pseudo-disaster conditions. The test standards and methods, developed along with the system, are also presented.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.110-119
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• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.349-352
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• 2000

In this paper, a SIMD 64bit MAC (Multiply -Accumulate) unit is designed. It is composed of two 32bit MAC unit which supports SIMD 16bit operations. As a result, It can process two 32bit MAC operations or four 16bit operations in one cycle. Proposed MAC unit is described in Verilog HDL. After functional verification is performed, MAC unit is synthesized and optimized with 0.35$\mu\textrm{m}$ standard cell library. The synthesis result shows that this MAC unit can operate at 80㎒ of clock frequency in 85$^{\circ}C$, 3.0V, worst case process and 125㎒ of clock frequency at 25$^{\circ}C$, 3.3V, typical case process. It achieves 320Mops of performance, and is suitable for embedded DSP processors.

• ETRI Journal
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• v.28 no.3
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• pp.397-400
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• 2006

The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.107-112
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• 2012

In this contribution, we designed a general purpose input/output (GPIO) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. General purpose I/O should be used as multi-functional and versatile interrupt sources. We considered the edge-sensitive mode as well as the level-sensitive mode for acquiring the interrupt sources. Also, we provided an option to select the operation polarity for flexible application to the embedded systems. The designed GPIO module was automatically synthesized, placed, and routed. The proposed GPIO was implemented through the Altera FPGA and well operated at 25MHz clock frequency.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.454-461
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• 2007

Portable embedded systems have recently become smaller in size and offer a variety of junctions for users. These systems require high performance processors to handle the many functions and also a small battery to fit inside the system. However, due to its size, the battery life has become a major issue. It is important to have both efficient power design and management for each function, while optimizing processor voltage and clock frequency in order to extend the battery life of the system. In this paper, we calculated the efficiency of power in optimizing power rail. This system has two microprocessors. One is used to play music and movie files while the other is for DMB. In order to reduce power consumption, the DMB microprocessor is turned of while music or videos are played. Lastly, DVFS is applied to the processor in the system to reduce power consumption. Experimental results of the implemented system have resulted in reduced power consumption.