• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.793-796
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• 2005

A structure and a design of device were developed to fabricate large-scale active matrix organic light-emitting diode (AMOLED) display with good color purity and high aperture ratio. With these technologies, we developed a full color 14.1 inch WXGA AMOLED display. For the integration of OLED on an active matrix a-Si TFT backplane, an efficient top emission OLED is essential since the TFT circuitry covers a large position of the pixel aperture. These technologies will enable up the OLED applications to larger size displays such as desktop monitors and TVs.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.954-957
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• 1987

This paper proposes a kind of function-concentrated signaling service equipment structure, in which various kind of signaling service are efficiently made for call processing control. Based upon the typical switching system models, a philosophical study on the capacity, features of structure in world systems, and interfaces with peripheral equipments has been performed in order to provide the rationale on the merits or efficiency of the proposed digital signaling service equipment.

• ETRI Journal
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• 제29권1호
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• pp.59-69
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• 2007

We designed and fabricated a vision chip for edge detection with a $160{\times}120$ pixel array by using 0.35 ${\mu}m$ standard complementary metal-oxide-semiconductor (CMOS) technology. The designed vision chip is based on a retinal structure with a resistive network to improve the speed of operation. To improve the quality of final edge images, we applied a saturating resistive circuit to the resistive network. The light-adaptation mechanism of the edge detection circuit was quantitatively analyzed using a simple model of the saturating resistive element. To verify improvement, we compared the simulation results of the proposed circuit to the results of previous circuits.

• Journal of Power Electronics
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• 제12권6호
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• pp.947-953
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• 2012

The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.18um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated.

• 대한전자공학회논문지TC
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• 제39권11호
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• pp.34-39
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• 2002

본 논문에서는 마이크로스트립 전송선로의 유전체 기판(substrate) 내에 삽입된 EGP(Elevated Ground Plane)와 비아를 이용하는 소형의 새로운 포토닉 밴드갭(PBG：Photonic Bandgap) 구조를 제안였하고, 세라믹 기판에 적용된 최적구조를 설계하였다. 해석 결과, 제안된 새로운 PBG 구조는 기존의 평면 PBG 구조에 비해서 크기가 52.5 % 축소되었고 대역폭은 45 % 증가하였다. 그리고 접지면 식각 다층 PBG 구조에 비해서는 크기가 32 % 감소하였고 첨예도(sharpness)가 향상되었으며 차단주파수 이상에서 40 GHz까지 전력손실이 8 dB 이상 개선되었다. 따라서 본 논문에서 제안된 PBG 구조는 대역 저지 또는 저역통과 여파기로 사용할 수 있으며, 이러한 여파기 특성은 경박 단소화된 마이크로파 대역 집적회로나 모듈 개발에 효과적으로 활용될 수 있으리라 기대된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.45-48
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• 2004

본 논문은 니켈실리사이드 (Ni-Silicide)의 열안정성을 개선하기 위해서 Ti와 TiN capping 층을 이용한 새로운 구조 Ni/Ti/Ni/Tin 구조를 제안하였다. 계면특성과 열안정성을 향상시키기 위해 타이타늄(Ti)을 니켈(Nickel) 사이에 적용하고, 니켈 실리사이드 형성 시 산소와의 반응을 억제하여 실리사이드의 응집현상을 개선시키고자 TiN capping을 적용 하였다. 니켈 실리사이드의 형성온도에 따른 $NiSi_2$로의 상변이를 억제할 수 있었고, 열안정성 평가를 위한 $700^{\circ}C$, 30분간 고온 열처리에서도 제안한 구조로 니켈실리사이드의 단면특성과 19 % 정도 면저항 특성을 개선하였다.

• 대한전자공학회논문지TC
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• 제38권12호
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• pp.39-48
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• 2001

본 논문에서는 마이크로스트립 라인에 포토닉 밴드갭(photonic bandgap: PBG) 구조를 구현할 경우 저지대역 내에 형성되는 통과대역의 부분대역폭(fractional bandwidth)을 효과적으로 조절할 수 있는 PBG 구조의 설계에 관하여 연구하였다. 이 구조는 결함을 갖는 통상적 PSG 구조의 기본 PSG 셀(cell)에 스텁(stub)을 더하여 구현한 것으로 PBG 셀에 첨가된 스텁 길이가 증가함에 따라 스컷(skirt) 특성이 현저하게 개선됨을 볼 수 있었다. 이때 차단주파수(cutoff- frequency), 저지대역 및 통과대역의 중심주피수는 저주파 쪽으로 이동하였고 통과대역폭은 감소하였다. 이러한 결과는 PBG 셀에 스텁을 활용함으로써 저지대역 내에 형성되는 통과대역의 부분대역폭을 효과적으로 조절할 수 있음을 보여준다. 또한 스텁을 갖는 PBG 구조를 응용하여 우수한 스컷 특성을 갖는 듀플렉서를 설계할 수 있음도 보였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.483-484
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• 2006

In this paper, we fabricated the organic bi-stable devices under the different condition from the other groups and analyzed the electrical characteristics. Then we investigated the effects of the device structure such as organic layer thickness, middle metal layer thickness and middle metal layer deposition rate on the memory characteristics.

• Journal of Power Electronics
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• 제11권6호
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• pp.870-879
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• 2011

Regulated peak power tracking (RPPT) systems such as the series structure and the series-parallel structures are commonly used in satellite space power systems. However, these structures process the solar array power or the battery power to the load through two cascaded regulators during one orbit cycle, which reduces the energy transfer efficiency. Also the battery charging time is increased due to placement of converter between the battery and the solar array. In this paper a parallel structure has been proposed which can improve the energy transfer efficiency and the battery charging time for satellite space power RPPT systems. An analogue controller is used to control all of the required functions, such as load voltage regulation and solar array stabilization with maximum power point tracking (MPPT). In order to compare the system efficiency and the battery charging efficiency of the proposed structure with those of a series (conventional) structure and a simplified series-parallel structure, simulations are performed and the results are analyzed using a loss analysis model. The proposed structure charges the battery more quickly when compared to the other two structures. Also the efficiency of the proposed structure has been improved under different modes of solar array operation when compared with the other two structures. To verify the system, experiments are carried out under different modes of solar array operation, including PPT charge, battery discharge, and eclipse and trickle charge.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2006년도 춘계학술대회 학술발표 논문집 제16권 제1호
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• pp.125-129
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• 2006

By advent of NNC(Neural Network Chip), it is possible that process in parallel and discern the importance of signal with learning oneself by experience in external signal. So, the design of general purpose operation unit using VHDL(VHSIC Hardware Description Language) on the existing FPGA(Field Programmable Gate Array) can replaced EN(Expert Network) and learning algorithm. Also, neural network operation unit is possible various operation using learning of NN(Neural Network). This paper present general purpose operation unit using hierarchical structure of EN. EN of presented structure learn from logical gate which constitute a operation unit, it relocated several layer. The overall structure is hierarchical using a module, it has generality more than FPGA operation unit.