• The monthly packaging world
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• s.255
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• pp.61-67
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• 2014

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.184-184
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• 2008

저온 동시 소성 세라믹(LTCC, Low Temperature Co-firing) 기술 중에서 테이프 캐스팅(tape casting)은 얇고 균일한 세라믹 그린 쉬트를 연속 성형할 수 있으며 성형된 쉬트의 밀도, 표면상태, 두께제어 등이 매우 중요하다. 얇고 균일한 세라믹 그린 쉬트를 제작하기 위해서 슬러리의 분산성과 레오로지 특성은 매우 중요한 요소이며 첨가되는 유기물 첨가제들의 종류와 함량비는 슬러리의 분산성과 점도에 큰 영향을 미친다. 본 연구에서는 유기물 첨가제의 종류와 함량에 따른 슬러리의 점도와 그린 쉬트의 밀도 및 두께 제어에 미치는 영향을 고찰하였다. 바인더로는 acryl, polyvinyl 계를 사용하였으며, 가소제는 glycol, phatalate 계를 사용하였다. 각각 2 종류의 바인더와 가소제의 함량에 따른 레올로지 거동과 그런 쉬트의 밀도를 측정하였다. 각 조성별로 준비된 슬러리를 사용하여 테이프 캐스팅 방법으로 제작된 그린 쉬트의 두께를 측정하여 유기물 첨가제 조성이 그린 쉬트의 두께제어에 미치는 영향을 평가하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.275-276
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• 2008

통신기기가 고주파수화 함에 따라서 저유전 저손실 재료의 필요성이 증대되고 있으며, 세라믹/폴리머 복합재료를 고주파 회로 기판 소재로 이용하려는 관심이 증폭되고 있다. 본 연구에서는 저손실, 저유전율 특성을 구현하기 위해 $SiO_2$를 세라믹 필러로 복합물을 제작하였다. 평균 입자 크기가 16nm, $2.3{\mu}m$의 fumed 실리카와 평균 입자 크기 $1{\mu}m$, $4{\mu}m$의 fused 실리카를 사용하였다. 이 4종류 실리카를 사용하여 slurry를 제작하고 이를 활용하여 tape을 제작하였다. 제작된 복합체 tape을 적층하여 기판을 제작해 기판의 유전특성을 측정하였다. fumed 실리카의 경우 $SiO_2$ 10vol%이상에서는 균일한 tape성형이 어려워졌으며, 유전 손실이 fused 실리카와 비교하였을 때 큰 폭으로 증가하였다. fumed silica, fused silica 두 종류 모두 입도가 증가하면 유전손실이 증가하였다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.73-73
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• 2004

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.9-17
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• 2017

In these days, MEMS (micro-electro-mechanical system) devices become the crucial sensor components in mobile devices, automobiles and several electronic consumer products. For MEMS devices, the packaging determines the performance, reliability, long-term stability and the total cost of the MEMS devices. Therefore, the packaging technology becomes a key issue for successful commercialization of MEMS devices. As the IoT and wearable devices are emerged as a future technology, the importance of the MEMS sensor keeps increasing. However, MEMS devices should meet several requirements such as ultra-miniaturization, low-power, low-cost as well as high performances and reliability. To meet those requirements, several innovative technologies are under development such as integration of MEMS and IC chip, TSV(through-silicon-via) technology and CMOS compatible MEMS fabrication. It is clear that MEMS packaging will be key technology in future MEMS. In this paper, we reviewed the recent development trends of the MEMS packaging. In particular, we discussed and reviewed the recent technology trends of the MEMS bonding technology, such as low temperature bonding, eutectic bonding and thermo-compression bonding.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.45-49
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• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• Transactions on Electrical and Electronic Materials
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• v.11 no.4
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• pp.178-181
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• 2010

An automotive IC voltage regulator which consists of one-chip based on a metal-oxide semiconductor field effect transistor (MOSFET) is investigated experimentally with three types of packaging. The closed type is filled with thermal silicone gel and covered with a plastic lid on the MOSFET. The half-closed type is covered with a plastic case but without thermal silicone gel on the MOSFET. Opened type is no lid without thermal silicone gel. In order to simulate the high temperature condition in engine bay, the operating circuit of the MOSFET is constructed and the surrounding temperature is maintained at $100^{\circ}C$. In the overshoot the maximum was mainly found at the half-closed packaging and the magnitude is dependent on the packaging type and the surrounding temperature. Also the impressed current decreased exponentially during the MOSFET operation.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.1-5
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• 2012

The quality and performance of electronic parts and equipment are affected by various types of stresses. Thermal stress caused by changes in the ambient usage environment and mechanical stress from vibration shock during transportation can degrade both quality and performance. This paper gives an overview about recent researches for measuring market environmental conditions of electronic equipments.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.07a
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• pp.63-92
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• 2001

·EC's/Japanese environmental regulation drive the Pb-free/Halogen-free application ·Most Japanese electronics companies are preparing the green products. ·All items concerning to Pb-free/halogen-free technology should be coparallely designed and developed. ·More works need to clear the unknowns on Pb-free materials ·Need of consensus on materials and standards ·EBM (Environmental Benign Manufacturing)