• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.6
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• pp.96-103
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• 1999

This paper proposes efficient VLSI architecture for computation of the 1-D discrete wavelet transform (DWT). The proposed VLSI architecture computes the wavelet lowpass and highpass output sequences using the product term anhm, $n,m{\ge}0$, where an and hm denote the imput sequence and the wavelet lowpass filter coefficient, respectively. Whereas the conventional architectures compute the lowpass and highpass output sequences using the product terms anhm and angm, respectively, where gm denotes the wavelet highpass filter coefficient. The proposed architecture is applied to computation of the Daubechies 4-tap wavelet transform using the relationships between the Daubechies wavelet filter coefficients. Performance comparison of various architectures for computation of the 1-D DWT are presented. Note that the proposed architecture does not require extra processing units whereas the conventional architectures need them. Also it is modeled in very high speed integrated circuit hardware description language (VHDL) and simulated to show its functional validity.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.6
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• pp.33-37
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• 1980

The information display control system is designed and implemented on an automobile in which the conventional panel displays are replaced by electronic ones. The system hardware consists of three main parts, i. e., (i) the function select keyboard (ii) the central processing unit (iii) the displays, The system software consists of main routine and several interrupt service routine such as keyboaiuand display interrupt service routine:. The main routine handles various sensor inputs to generate the appropriate information for the driver such as running speed, available fuel quantity. coolant temperature, battery voltage, remaining distance to the destination , time of day, and so on. Finally the results of the field test of the system and some associated difficulties of realization problems are discussed.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.67-74
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• 2015

BTC (Block Truncation Coding) image compression is simple to implement by hardware and has excellent edge retention capability of image, image compression techniques are widely used in LCD overdrive. In this paper, to maintain high visual quality and has high compression rate, Multi-Mode BTC (MM-BTC) algorithm is proposed. The MM-BTC has high compression rate using advanced Y-based BTC method and has high visual quality using improved 2-level and 4-level BTC method in this paper. As shown in simulation results, MM-BTC improves still image PSNR (Peak Signal to Noise Ratio) up to 2.34 dB as compared with other algorithms. When the MM-BTC is applied to LCD overdrive, MM-BTC improves moving picture PSNR up to 2.33 dB as compared with other algorithms in literature.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.45-53
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• 2015

Adaptive support-weight based algorithm can produce better disparity map compared to generic area-based algorithms and also can be implemented as a realtime system. In this paper, we propose a realtime system based on geodesic support-weight which performs better segmentation of objects in the window. The data scheduling is analyzed for efficient hardware design and better performance and the parallel architecture for weight update which takes the longest delay is proposed. The exponential function is efficiently designed using a simple step function by careful error analysis. The proposed architecture is designed with verilogHDL and synthesized using Donbu Hitek 0.18um standard cell library. The proposed system shows 2.22% of error rate and can run up to 260Mhz (25fps) operation frequency with 182K gates.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.4
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• pp.347-350
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• 2017

In this paper, we implemented a real-time 2.4 GHz direction finding system using a time-modulated array(TMA) and an Universal Software Radio Peripheral(USRP). Our system consists of two commercial monopole antennas, self-designed switch board, and an USRP, and it is controlled using LabVIEW program in real-time. From measured results, it is verified that our system can exactly detect the incident angle within 4 degree in the range of 30 degree. Our direction finding system has advantages of a simple hardware architecture than conventional one with multiple receivers, and a simple algorithm only by using a main lobe and a first side-lobe of switching frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.170-178
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• 2004

In this work a high speed 8-error correcting Reed-Solomon decoder is designed using the modified Euclid algorithm. Decoding algorithm of Reed-Solomon codes consists of four steps, those are, compute syndromes, find error-location polynomials, decide error-locations, and determine error values. The decoding speed is increased and the latency is reduced by using the parallel architecture in the syndrome generator and a faster clock speed in the modified Euclid algorithm block. In addition. the error locator polynomial in Chien search block is separated into even and odd terms to increase the overall speed of the decoder. All the functionalities of the decoder are verified first through C++ programs. Verilog is used for hardware description, and then the decoder is synthesized with a $.25{\mu}m$ CMOS TML library. The functionalities of the chip is also verified through test vectors. The clock speed of the chip is 250MHz, and the maximum data rate is 1Gbps.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.757-759
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• 2013

Until just a few years ago, digital circuit design techniques in register transfer level using Verilog or VHDL have been recognized as the up-to-date way compared with the traditional schematic design, and truly they have been used as the most popular skill for most chip designs. However, with the advent of era in which the complexity of semiconductor chip counts over billion transistors with advanced manufacturing technology, designing in register transfer level became too complex to meet the requirements of the needs, so the design paradigm has to change so that both design and synthesis can be done in higher level of abstraction. Bluespec SystemVerilog (BSV) is the only HDL which enables both circuit design and generating synthesizable code in the system level developed so far. In this contribution, I survey and analyze the features which supports the new paradigm in the BSV HDL, not very familiar to industry yet.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.345-348
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• 2013

This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.10
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• pp.579-584
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• 2014

In this paper, we propose beamsapce MIMO(mulitple input multiple output) system using patch ESPAR(Electronically Steerable Parasitic Array Radiator) antenna. When using conventional monopole ESPAR antenna, we have advantages cost of hardware and power consumption of RF cirsuit because of single RF chian. But it is difficult to apply to small portable mobile device. Therefore we design patch ESPAR antenna in order to reducing volume and analyze performance of BS MIMO system that is able to MIMO communication with single RF chain. In This paper, we confirm beam pattern of designed patch ESPAR antenna is steered as ${\pm}15^{\circ}$ elevation angle. Furthermore, we design BS MIMO system using this ESPAR antenna and confirm BER performance of this system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.8
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• pp.740-747
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• 2015

Recently, mobile communication systems using the millimeter-wave frequency band have been proposed, and the importance of efficient compensation of the nonlinearity caused by 60 GHz high-power amplifiers(HPAs) is increasing. In this paper, we propose a predistorter structure based on multiple coefficient sets which are separately used to different ranges of input power values. These ranges correspond to varying levels of nonlinearity characteristics. The structure is applied to the 60 GHz HPA FMM5715X and the performance of correcting the nonlinearity of LTE signals is evaluated. Evaluation results using a hardware testbed demonstrate that the proposed predistorter structure achieves the maximum of 6 dB gain over the conventional method in terms of the adjacent channel leakage ratio(ACLR).