• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.902-905
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• 2004

A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUID) sensors for precision MCG signal acquisitions. Such system is composed of hundreds of sensors, requiring fast signal sampling and precise analog-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit 1ks/s, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 ms speed. The test result shows that the signal acquisition is done in 168 usuc which is much shorter than the required 1 ms period. This hardware will be extended to 256 channel data acquisition to be used for the diagnosis system.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1210-1216
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• 2003

Recently, as the road capacity reaches the limit and environmental problems becomes serious, there is gradually increased a need for railroad vehicles that are environment-friendly and have time regularity, reliability, and safety. Accordingly, in addition to conventional railroad vehicles, lots of vehicles are being newly developed. We developed the hardware and software of the measurement system for on-line test and evaluation of korean high speed train. The software controls the hardware of the measurement system and acts as interface between users and the system hardware. In this paper, practical experiment are performed to verify mechanical performance of motor and main transformer for Korean high speed rail. The experimental test carried out by using new temperature measurement method and verify the temperature performance of motor and transformer is verified.

• Proceedings of the KSME Conference
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• 2001.06b
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• pp.741-746
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• 2001

This paper presents an investigation of a vehicle-to-vehicle distance control using a Hardware-in-the-Loop Simulation(HiLS) system. Since vehicle tests are costly and time consuming, how to establish a efficient and low cost development tool is an important issue. The HiLS system consists of a stepper motor, an electronic vacuum booster, a controller unit and two computers which are used to form real time simulation and to save vehicle parameters and signals of actuator through a CAN(Controller Area Network). Adoption of a CAN for communication is a trend in the automotive industry. Since this environment is the same as that of a real vehicle, a distance control logic verified in laboratory can be easily transfered to a test vehicle.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.636-639
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• 2004

In present, there are many methods such as DCT, Wavelet Transform, or Quantization -to the image compression field, but the basic image compression method have based on DCT. The representative thing of the efficient techniques for information compression is DCT method. It is more superior than other information conversion method. It is widely applied in digital signal processing field and MPEG and JPEG which are selected as basis algorithm for an image compression by the international standardization group. It is general that DCT is consisted of using multiplier with main arithmetic blocks having many arithmetic amounts. But, the use of multiplier requires many areas when hardware is embodied, and there is fault that the processing speed is low. In this paper, we designed the hardware module that could run high-speed operation using row-column separation calculation method and Chen algorithm by distributed arithmetic method using ROM table instead of multiplier for design DCT module of high speed.

• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.39-45
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• 2009

In this paper, we discuss hardware design and deployment issues in current passive UHF RFID systems. Using the link budget concept, the methodology to calculate forward- and reverse-link interrogation range is shown. Then, we consider hardware issues: phase diversity, phase noise with range correlation, and TX leakage problems. Finally, three interference problems when deploying RFID systems are presented.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.11
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• pp.5370-5393
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• 2019

In this paper, we consider a two-way relay non-orthogonal multiple access (TWR-NOMA) system with residual hardware impairments (RHIs) and channel estimation errors (CEEs), where two group users exchange their information via the decode-and-forward (DF) relay by using NOMA protocol. To evaluate the performance of the considered system, exact analytical expressions for the outage probability of the two groups users are derived in closed-form. Moreover, the asymptotic outage behavior in the high signal-to-noise ratio (SNR) regime is examined and the diversity order is derived and discussed. Numerical simulation results verify the accuracy of theoretical analyses, and show that: i) RHIs and CEEs have a deleterious effects on the outage probabilities; ii) CEEs have significant effects on the performance of the near user; iii) Due to the RHIs, CEEs, inter-group interference and intra-group interference, there exists error floors for the outage probability.

• Journal of IKEEE
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• v.19 no.2
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• pp.254-259
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• 2015

CABAC is a context-based adaptive binary arithmetic coding method. It increases the encoding efficiency by updating the probability based on the information of the previously coded symbols. Context modeler is a core block of CABAC, which designs a probability model according to the symbol considering statistical correlations. In this paper, an efficient hardware architecture of CABAC context modeler is proposed. The proposed context modeler was designed in Verilog HDL and it was implemented in 0.18 um technology. Its gate count is 29,832 gates including memory. Its operating speed and throughput are 200 MHz and 200 Mbin/s, respectively.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.237-237
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• 2004

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.233-233
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• 2004

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.888-894
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• 2015

This paper describes an efficient hardware design of Lightweight Encryption Algorithm (LEA) developed by National Security Research Institute(NSRI). The LEA crypto-processor supports for master key of 128-bit. To achieve small-area and low-power implementation, an efficient hardware sharing is employed, which shares hardware resources for encryption and decryption in round transformation block and key scheduler. The designed LEA crypto-processor was verified by FPGA implementation. The LEA core synthesized with Xilinx ISE has 1,498 slice elements, and the estimated throughput is 216.24 Mbps with 135.15 MHz.