• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.12
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• pp.1688-1696
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• 2020

The paradigm of Internet-of-things(IoT) systems is changing from a cloud-based system to an edge-based system to solve delays caused by network congestion, server overload and security issues due to data transmission. However, edge-based IoT systems have fatal weaknesses such as lack of performance and flexibility due to various limitations. To improve performance, application-specific hardware can be implemented in the edge device, but performance cannot be improved except for specific applications due to a fixed function. This paper introduces a edge-centric metamorphic IoT(mIoT) platform that can use a variety of hardware through on-demand partial reconfiguration despite the limited hardware resources of the edge device, so we can increase the performance and flexibility of the edge device. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to previous studies in which the reconfiguration algorithm was executed on the server.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.670-673
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• 2008

Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.669-678
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• 2002

Currently, the domestic interests on the development of eyesight related measuring instruments are being increased. So we are developing such an electronic system of Refracto-keratometer, which contains a software and a hardware both. If this system could inform the examiner of the precise eyesight measuring result from the treatment of the image of optical system, then potentially the number of missed measuring results could be reduced. Our electronic system has been developed from the two areas divided into a software and a hardware. The software area was focused on the more exact eyesight measuring results, using morphological filtering methods and gray-leveled signal enhancing techniques. The hardware area is performing the same functions as the existing other systems. Besides, it provides the embedded software with free variables which could reduce the developing duration sharply as well as enlarge many kinds of application-extensions. Therefore, this electronic system has made effective eyesight measurement possible as the result of reducing the differences applied to sophisticated eyesight measurement.

• Journal of Biomedical Engineering Research
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• v.28 no.6
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• pp.803-810
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• 2007

Although synthetic aperture focusing techniques can improve the spatial resolution of ultrasound imaging, they have not been employed in a commercial product because they require a real-time N-channel beamformer with a tremendously increased hardware complexity for simultaneous beamforming along M multiple lines. In this paper, a hardware-efficient beamformer architecture for synthetic aperture focusing is presented. In contrast to the straightforward design using NM delay calculators, the proposed method utilizes only M delay calculators by sharing the same values among the focusing delays which should be calculated at the same time between the N channels for all imaging points along the M scan lines. In general, synthetic aperture beamforming requires M 2-port memories. In the proposed beamformer, the input data for each channel is first upsampled with a 4-fold interpolator and each polyphase component of the interpolator output is stored into a 2-port memory separately, requiring 4M 2-port memories for each channel. By properly limiting the area formed with the synthetic aperture focusing, the input memory buffer can be implemented with only 4 2-port memories and one short multi-port memory.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1851-1860
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• 2016

The traction motors in electric multiple unit (EMU) trains are powered by AC-DC-AC converters, and the DC link voltage is generated by single phase PWM converters, with a fluctuation component under twice the frequency of the input catenary AC grid, which causes fluctuations in the motor torque and current. Traditionally, heavy and low-efficiency hardware LC resonant filters parallel in the DC side are adopted to reduce the ripple effect. In this paper, an analytical model of the ripple phenomenon is derived and analyzed in the frequency domain, and a ripple control scheme compensating the slip frequency of rotor vector control systems without a hardware filter is applied to reduce the torque and current ripple amplitude. Then a relatively simple discretization method is chosen to discretize the algorithm with a high discrete accuracy. Simulation and experimental results validate the proposed ripple control strategy.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.131-134
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• 2007

In this paper, we propose the 1D-CZP pattern for FPGA verification. The algorithm that was implemented by Verilog-HDL on FPGA board is verified before the chip is producted. Input through the external sensor might not be enough to verify the algorithm on FPGA board. Hence, both external input and internal input can lead the verification of the algorithm. This paper suggests the hardware implementation of compact 1D-CZP pattern that has the random input. It is useful to analyze the characteristics of the filter frequencies and organized as ROM Table which is efficient to Modulus operation.

• Journal of Korean Society of Archives and Records Management
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• v.7 no.1
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• pp.145-170
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• 2007

Unlike paper records, accessing electronic records needs to be supported by specific combination of hardware and software. The electronic records have longer life span than the storage media, hardware, software and the formats that were used for the production of such records. Because the quality of electronic record can become deteriorated as time goes on, we need to have appropriate mechanisms to secure the long-term preservation and access to the digital information at a certain point in the future. Based on this reality, this study proposes the functions and the development method of the format registry, which efficiently supports the preservation strategy such as migration and emulation, collecting and managing technical information elements. These elements consist of the foundation of the long-term preservation of the electronic records.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.91-94
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• 2012

This paper describes an efficient implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit specified in the standard. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 33,218 gates and the estimated throughput is about 640 Mbps at 100 MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.425-437
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• 2017

For efficient hardware (HW) implementation of elliptic curve cryptography (ECC), various sub-modules for the underlying finite field operations should be implemented efficiently. Among these sub-modules, modular inversion (MI) requires the most computation; therefore, its performance might be a dominant factor of the overall performance of an ECC module. To determine the most efficient MI algorithm for an HW ECC module, we implement various classes of MI algorithms and analyze their performance. In contrast to the common belief in previous research, our results show that the right-shift binary inversion (RS) algorithm performs well when implemented in hardware. In addition, we present optimization methods to reduce the area overhead and improve the speed of the RS algorithm. By applying these methods, we propose a new RS-variant that is both fast and compact. The proposed MI module is more than twice as fast as the other two classes of MI: shifting Euclidean (SE) and left-shift binary inversion (LS) algorithms. It consumes only 15% more area and even 5% less area than SE and LS, respectively. Finally, we show that how our new method can be applied to optimize an HW ECC module.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.5
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• pp.967-971
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• 2009

The histogram equalization algorithm is the most crucial algorithm for image enhancement. Since its direct hardware implementation always requires a divider or multiplier, its implementation cost tends to increas as the image resolution is increased or diverse image resolutions are handled. In this paper, we propose a divider-free reconstruction of histogram equalization algorithm and the corresponding hardware architecture. The logic synthesis results show that the proposed scheme can reduce the logic gate count by 84.2% compared to the conventional implementation example when the UXGA resolution is considered.