• 제목/요약/키워드: Electronic Hardware

검색결과 1,036건 처리시간 0.028초

심자도 신호 획득을 위한 실시간 64-Ch 12-bit 1ks/s 하드웨어 개발 (Development of 64-Channel 12-bit 1ks/s Hardware for MCG Signal Acquisition)

  • 이동하;유재택
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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    • pp.902-905
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    • 2004
  • A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUID) sensors for precision MCG signal acquisitions. Such system is composed of hundreds of sensors, requiring fast signal sampling and precise analog-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit 1ks/s, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 ms speed. The test result shows that the signal acquisition is done in 168 usuc which is much shorter than the required 1 ms period. This hardware will be extended to 256 channel data acquisition to be used for the diagnosis system.

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고속철도차량용 전기장치의 온도특성에 관한 연구 (A Study on Temperature Characteristics of Electric Apparatuses for High Speed Train)

  • 한영재;양도철;장호성;최종선;김정수
    • 한국전기전자재료학회논문지
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    • 제16권12S호
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    • pp.1210-1216
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    • 2003
  • Recently, as the road capacity reaches the limit and environmental problems becomes serious, there is gradually increased a need for railroad vehicles that are environment-friendly and have time regularity, reliability, and safety. Accordingly, in addition to conventional railroad vehicles, lots of vehicles are being newly developed. We developed the hardware and software of the measurement system for on-line test and evaluation of korean high speed train. The software controls the hardware of the measurement system and acts as interface between users and the system hardware. In this paper, practical experiment are performed to verify mechanical performance of motor and main transformer for Korean high speed rail. The experimental test carried out by using new temperature measurement method and verify the temperature performance of motor and transformer is verified.

차간거리제어 Hardware-in-the-Loop 시뮬레이션 (Hardware-in-the-Loop Simulation of a Vehicle-to-Vehicle Distance Control System)

  • 문일기;이찬규;이경수;권영도
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2001년도 춘계학술대회논문집B
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    • pp.741-746
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    • 2001
  • This paper presents an investigation of a vehicle-to-vehicle distance control using a Hardware-in-the-Loop Simulation(HiLS) system. Since vehicle tests are costly and time consuming, how to establish a efficient and low cost development tool is an important issue. The HiLS system consists of a stepper motor, an electronic vacuum booster, a controller unit and two computers which are used to form real time simulation and to save vehicle parameters and signals of actuator through a CAN(Controller Area Network). Adoption of a CAN for communication is a trend in the automotive industry. Since this environment is the same as that of a real vehicle, a distance control logic verified in laboratory can be easily transfered to a test vehicle.

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A Study on the Design of DCT Module using Distributed Arithmetic Method

  • Yang Dong Hyun;Ku Dae Sung;Kim Phil Jung;Yon Jung Hyun;Kim Sang Duk;Hwang Jung Yeun;Jeong Rae Sung;Kim Jong Bin
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 학술대회지
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    • pp.636-639
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    • 2004
  • In present, there are many methods such as DCT, Wavelet Transform, or Quantization -to the image compression field, but the basic image compression method have based on DCT. The representative thing of the efficient techniques for information compression is DCT method. It is more superior than other information conversion method. It is widely applied in digital signal processing field and MPEG and JPEG which are selected as basis algorithm for an image compression by the international standardization group. It is general that DCT is consisted of using multiplier with main arithmetic blocks having many arithmetic amounts. But, the use of multiplier requires many areas when hardware is embodied, and there is fault that the processing speed is low. In this paper, we designed the hardware module that could run high-speed operation using row-column separation calculation method and Chen algorithm by distributed arithmetic method using ROM table instead of multiplier for design DCT module of high speed.

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Hardware Design and Deployment Issues in UHF RFID Systems

  • Jang, Byung-Jun;Yoon, Hyun-Goo;Lim, Jae-Bong
    • Journal of electromagnetic engineering and science
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    • 제9권1호
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    • pp.39-45
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    • 2009
  • In this paper, we discuss hardware design and deployment issues in current passive UHF RFID systems. Using the link budget concept, the methodology to calculate forward- and reverse-link interrogation range is shown. Then, we consider hardware issues: phase diversity, phase noise with range correlation, and TX leakage problems. Finally, three interference problems when deploying RFID systems are presented.

Performance Analysis of Two-Way Relay NOMA Systems with Hardware Impairments and Channel Estimation Errors

  • Tian, Xinji;Li, Qianqian;Li, Xingwang;Zhang, Hui;Rabie, Khaled;Cavalcante, Charles Casimiro
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제13권11호
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    • pp.5370-5393
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    • 2019
  • In this paper, we consider a two-way relay non-orthogonal multiple access (TWR-NOMA) system with residual hardware impairments (RHIs) and channel estimation errors (CEEs), where two group users exchange their information via the decode-and-forward (DF) relay by using NOMA protocol. To evaluate the performance of the considered system, exact analytical expressions for the outage probability of the two groups users are derived in closed-form. Moreover, the asymptotic outage behavior in the high signal-to-noise ratio (SNR) regime is examined and the diversity order is derived and discussed. Numerical simulation results verify the accuracy of theoretical analyses, and show that: i) RHIs and CEEs have a deleterious effects on the outage probabilities; ii) CEEs have significant effects on the performance of the near user; iii) Due to the RHIs, CEEs, inter-group interference and intra-group interference, there exists error floors for the outage probability.

HEVC CABAC 문맥 모델러의 하드웨어 구현 (Hardware Implementation of HEVC CABAC Context Modeler)

  • 김두환;문전학;이성수
    • 전기전자학회논문지
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    • 제19권2호
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    • pp.254-259
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    • 2015
  • CABAC은 문맥 기반 적응적 이진 산술 부호화 방식으로, 이전까지 부호화 된 심볼들의 정보를 이용하여 확률을 업데이트하여 부호화 효율을 높이는 기법이다. 문맥 모델러는 통계적 상관성을 고려하여 심볼에 따라 확률 모델을 설계하는 CABAC의 핵심 블록으로서, 본 논문에서는 문맥 모델러의 효율적인 하드웨어 아키텍쳐를 제안한다. Verilog HDL로 기술되어 0.18 um 공정으로 설계된 문맥 모델러는 메모리를 포함하여 29,832개의 게이트로 이루어져 있으며, 최대 동작속도는 200 MHz, 최대 처리율은 200 Mbin/s이다.

128비트 경량 블록암호 LEA의 저면적 하드웨어 설계 (A Small-area Hardware Design of 128-bit Lightweight Encryption Algorithm LEA)

  • 성미지;신경욱
    • 한국정보통신학회논문지
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    • 제19권4호
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    • pp.888-894
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    • 2015
  • 국가보안기술연구소(NSRI)에서 개발된 경량 블록암호 알고리듬 LEA(Lightweight Encryption Algorithm)의 효율적인 하드웨어 설계에 대해 기술한다. 마스터키 길이 128비트를 지원하도록 설계되었으며, 라운드 변환블록과 키 스케줄러의 암호화 연산과 복호화 연산을 위한 하드웨어 자원이 공유되도록 설계하여 저전력, 저면적 구현을 실현했다. 설계된 LEA 프로세서는 FPGA 구현을 통해 하드웨어 동작을 검증하였다. Xilinx ISE를 이용한 합성결과 LEA 코어는 1,498 슬라이스로 구현되었으며, 135.15 MHz로 동작하여 216.24 Mbps의 성능을 갖는 것으로 평가 되었다.