• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.34-41
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• 2002

This paper describes a scalable implementation method of a word-based RSA cryptoprocessor using pseudo carry look-ahead adder The basic organization of the modular multiplier consists of two layers of carry-save adders (CSA) and a reduced carry generation and Propagation scheme called the pseudo carry look-ahead adder for the high-speed final addition. The proposed modular multiplier does not need complicated shift and alignment blocks to generate the next word at each clock cycle. Therefore, the proposed architecture reduces the hardware resources and speeds up the modular computation. We implemented a single-chip 1024-bit RSA cryptoprocessor based on the word-based modular multiplier with 256 datapaths in 0.5${\mu}{\textrm}{m}$ SOG technology after verifying the proposed architectures using FPGA with PCI bus.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.1
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• pp.14-19
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• 2001

When the high power transistor is used for amplifier in microwave frequency, the bias of transistor is usually AB-class or B-c1ass because of power efficiency. The sweet spot point having small IMD signal compared with near neighborhood exicts frequently in the high power transistor using AB class bias or B-class bias. On the sweet spot, the magnitude and phase of the main and IMD signal of HPA output change as the input signal power change, respective the relative phase on the sweet spot changes rapidly. If we know exactly the magnitude and phase characteristics of IMD signal, we can design a more adequate linearizer and understand the characteristics of transistor. In this paper the magnitude and phase of the main and IMD signal of HPA output on the sweet spot are measured using the designed hardware.

• Journal of the Korean Data and Information Science Society
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• v.27 no.4
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• pp.887-898
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• 2016

The purpose of this study is to improve the learning ability of probability/statistics for H/W majors. Firstly, we developed a teaching method coupling probability/statistics with programming and multimedia signal processing courses that are opened in the H/W major curriculum. By use of its teaching-learning, we tried to verify the effectiveness on the improvement of learner's academic achievement and then analyze its educational efficiency through the regression analysis. Secondly, by analyzing the surveys and the statistical results of the education cases, we proposed a management plan on efficient teaching-learning in order to cultivate the learning ability of probability/statistics at a future time. Lastly, we concluded that probability/statistics is a required course of learners so as to contribute for the advanced technical development and the enhanced competitiveness in the field of the H/W.

• Journal of the Korean Institute of Intelligent Systems
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• v.27 no.2
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• pp.106-112
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• 2017

In the paper, we propose a levitation and a propulsion controller for the magnetic levitation logistic transportation system. The levitation controller is designed considering the mutual influence of the electromagnets to minimize roll and pitch movements. In order to solve the structural disadvantages of the magnetic levitation transportation system, we improve the problem of the existing controller by applying the exponential filter to the reference input. DSP-based control hardware is developed and the levitation control method is verified by levitation experiments to the air gap goal. The propulsion controller uses the space vector voltage modulation method. The propulsion controller is designed to follow the position and velocity profile by detecting the absolute position from the bar code information attached to the rail. The position control result shows satisfactory performance through the propulsion control reciprocating motion experiment.

• The Journal of Information Technology
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• v.5 no.4
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• pp.1-8
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• 2002

This thesis is about power line communication(PLC) over the low voltage grid. The main advantage with power line communication is the use of an existing infrastructure. The PLC channel can be modeled as having multi-path propagation with frequency-selective fading, typical power lines exhibit signal attenuation increasing with length and frequency. OFDM(Orthogonal Frequency Division Multiplexing) is a modulation technique where multiple low data rate carriers are combined by a transmitter to form a composite high data rate transmission. To implement the multiple carrier scheme using a bank of parallel modulators would not be very efficient in analog hardware. Each carrier in an OFDM is a sinusoid with a frequency that is an integer multiple of a base or fundamental sinusoid frequency. Therefore, each carrier is a like a Fourier series component of the composite signal. In fact, it will be shown later that an OFDM signal is created in the frequency domain, and then transformed into the time domain via the Discrete Fourier Transform(DFT).

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.1-10
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• 2006

Ubiquitous computing, a new type of network environment has been generating much interest recently and has been actively studied. In ubiquitous computing, the sensor network which consists of low electric power ad-hoc network-based sensors and sensor nodes, is particularly the most important factor The sensor network serves as the mediator between ubiquitous computing and the actual environment. Related studies are focused on network . management through lightweight hardware using RFID. However, to apply these to actual environment, more practical scenarios as well as more secured studies equipped with secures and efficiency features are needed. Therefore, this study aims to build a wireless network based on PTD for multi users, which provides the largest utility in individual networks, and propose an appropriate management method. The proposed method is designed to enhance security and efficiency related to various services required in wireless networks, based on the reliable peripheral devices for users or pm. using pm, which has been applied to electronic commerce transactions in existing papers, this study also proposed an appropriate management method that is suitable for a dynamic environment and setting a temporary group to provide various services.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.1-6
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.56-60
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• 2010

The widespread development of IT, growth of Web 2.0 application, the proliferation of personal hand held devices with access to the internet, and the availability of wireless networks, each have played an important role in creating the cloud computing model. Cloud computing is a business model and new trend of web application technology. The term is often used in the same context as grid computing or utility computing. In the cloud computing environment, we are able to use the same all of hardware resources in the server and share information easily. In this paper, we aimed a study to apply e-learning part to cloud computing environment. For this purpose, we proposed an application of LMS and LCMS based e-learning in the cloud computing environment. So LMS including LCMS connected to data center of cloud computing.

• Journal of IKEEE
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• v.21 no.1
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• pp.100-103
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• 2017

Motion estimation occupies the largest computation in the video compression. Multiple processing elements are often exploited in parallel to meet processing speed. More processing elements increase processing speed, but they also increase hardware area. therefore, it is important to optimize the number of processing element. HEVC (high efficiency video coding) usually exploits multi-stage motion estimation algorithms for low computation and high performance. Since the number and position of search points are different in each stage, the utilization of the processing elements is not always 100% and the utilization is quite different with the number of processing elements. In this paper, the optimizing method is proposed on the number of processing elements. It finds out the optimal number of the processing elements for the given multi-stage motion estimation algorithm by calculating utilization and execution cycle of the processing elements.