• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.7
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• pp.1401-1407
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• 2002

This paper represents an investigation of the vehicle-to-vehicle distance control system using Hardware-in-the-Loop Simulation(HiLS). Control logic is primarily developed and tested with a specially equipped test vehicle. Establishment of an efficient and low cost development tool is a very important issue, and test vehicle approach is costly and time consuming. HiLS method is useful in the investigation of driver assistance and active safety systems. The HiLS system consists of a stepper motor for throttle control, a hydraulic brake system with an electronic vacuum booster, an electronic controller unit, a data logging computer which are used to save vehicle states and signals of actuator through a CAN and a simulation computer using mathematical vehicle model. Adaptation of a CAN instead of RS-232 Serial Interface for communication is a trend in the automotive industry. Since this environment is the same as a test vehicle, a control logic verified in laboratory can be easily transferred to a test vehicle.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.100-103
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• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of IKEEE
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• v.23 no.3
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• pp.978-983
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• 2019

Under the influence of Autonomous Driving and AI, it is important to accurately recognize and judge objects through cameras. In particular, since a method of recognizing an object using a camera can obtain a large amount of information visually compared to other methods, many image signal processing methods have been studied to extract an accurate image. In addition, a lot of research is being carried out to implementation about hardware. In this work, we compare the principles and characteristics of the sorting algorithms that are frequently used in image signal processing and summarize the performance evaluation. Based on this, we define an efficient algorithm when implemented in hardware among efficient sorting algorithms.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.4
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• pp.214-220
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• 2007

Recently, most embedded systems have the multi-functions mixed the hardware with the software. The existing sequence programming methods are not suitable to implement the embedded system with multi-functions. So, it can be overcome the limit of a facility implementation by introducing the operating system in system. Also, due to the requirement about the better convenient and comfortable meeting or lecture environment, the necessity of electronic white-board is getting higher. Specially, the education using multimedia information is much more desirable for various and improved lecture at the high school and the university. But the sequence program which have been managed in existing electronic white-board system has some difficulties to achieve the software-oriented systems which has to accomplish many functions. In this paper, we propose the method to implement a facility of electronic white-board through using the embedded linux with excellent performance. The embedded linux presents the powerful software environment for the implementation of an embedded system and makes the realization of many various functions easy because it follows kernel characteristics of linux. In this paper, we describe the details for the structure of hardware, kernel source and device driver of a developed electronic white-board.

• Journal of IKEEE
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• v.15 no.1
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• pp.10-14
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• 2011

In this paper, we present an efficient hardware architecture of unrolling image mapper of catadioptric omnidirectional imaging systems. The catadioptric omnidirectional imaging systems generate images of 360 degrees of view and need to be transformed into panorama images in rectangular coordinate. In most application, it has to perform the panorama unrolling in real-time and at low-cost, especially for high-resolution images. The proposed hardware architecture adopts a software/hardware cooperative structure and employs several optimization schemes using look-up-table(LUT) of coordinate conversion. To avoid the on-line division operation caused by the coordinate transformation algorithm, the proposed architecture has the LUT which has pre-computed division factors. And then, the amount of memory used by the LUT is reduced to 1/4 by using symmetrical characteristic compared with the conventional architecture. Experimental results show that the proposed hardware architecture achieves an effective real-time performance and lower implementation cost, and it can be applied to other kinds of catadioptric omnidirectional imaging systems.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.4
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• pp.45-51
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• 2009

A hardware implementation of Hilbert transform is indespensible element in DSP system, but it suffers form a high complexity of system level hardware resulted in a large amount of the used gate. In this paper, we implemented the Hilbert transformer using MAG algorithm that reduces the complexity of hardware.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.1109-1112
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• 2020

This paper presents a low cost hardware message passing engine of enhanced atomic pipelined broadcast based on processing node status. In this algorithm, the previous atomic pipelined broadcast algorithm is modified to reduce the waiting time until next broadcast communication. For this, the processor change the transmission order of processing nodes based on the nodes' communication channel. Also, the hardware message passing engine architecture of the proposed algorithm is modified to be adopted to multi-core processor. The synthesized logic area of the proposed hardware message passing engine was reduced by about 16%, compared by the pre-existing hardware message passing engine.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.865-872
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• 2017

Recently, in response to the Internet age, the demand for hardware devices has been increasing, centering on the rapidly growing smart home field, due to the growth and management of sensor and control technology, mobile application, network traffic, big data management and cloud computing. In order to maintain the sustainable development of the hardware system, it is necessary to update the system, and the hardware device is absolutely necessary in real time processing of complex data (voice, image, etc.) as well as data collection. In this paper, we propose a method to simplify the control and communication method by integrating the hardware devices in two operating systems in a unified structure to solve the simultaneous control and communication method of hardware under different operating systems. The performance evaluation results of the proposed integrated hardware and the cloud control system connected to the cloud server are described and the main directions to be studied in the field of internet smart home are described.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.75-81
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• 2014

The integral image is the sum of input image pixel values. It is mainly used to speed up processing of a box filter operation, such as Haar-like features. However, large memory for integral image data can be an obstacle on an embedded hardware environment with limited memory resources. Therefore, an efficient method to store the integral image is necessary. In this paper, we propose a memory size reduction hardware design for integral image. The hardware design is used two methods. It is the new integral image memory and modulo calculation for reducing integral image data. The new integral image memory has additional calculation overhead, but it is not obstacle in hardware environment that parallel processing is possible. In the Xilinx Virtex5-LX330T targeted experimental result, integral image memory can be reduced by 50% on a $640{\times}480$ 8-bit gray-scale input image.

• Journal of the Korea Computer Graphics Society
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• v.23 no.3
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• pp.55-64
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• 2017

In this paper, a novel soft shadow method is suggested to support realistic shadows in mobile ray tracing. In ray tracing, soft shadow is generally generated by sampling a shadow ray. As this sampling method increases the number of rays to be processed, it has undermined the performance. We designed the proposed soft shadow processing method and hardware architecture to overcome this problem through selective shadow generation and triangle address caching for minimizing the performance degradation caused by sampling. The proposed hardware architecture can be integrated into a mobile ray-tracing hardware and was evaluated in terms of its performance on the FPGA. Based on the results, the rendering performance about 4, 8, and 16 samples were improved, respectively, by 40%, 50%, and 56% on average compared to the previous method, and it was found that the real-time soft shadow processing is feasible with the proposed hardware architecture.