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http://dx.doi.org/10.5573/ieie.2014.51.9.075

A Study of Integral Image Hardware Design for Memory Size Efficiency  

Lee, Su-Hyun (Department of Electronic Communication Engineering, Kwangwoon University)
Jeong, Yong-Jin (Department of Electronic Communication Engineering, Kwangwoon University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.9, 2014 , pp. 75-81 More about this Journal
Abstract
The integral image is the sum of input image pixel values. It is mainly used to speed up processing of a box filter operation, such as Haar-like features. However, large memory for integral image data can be an obstacle on an embedded hardware environment with limited memory resources. Therefore, an efficient method to store the integral image is necessary. In this paper, we propose a memory size reduction hardware design for integral image. The hardware design is used two methods. It is the new integral image memory and modulo calculation for reducing integral image data. The new integral image memory has additional calculation overhead, but it is not obstacle in hardware environment that parallel processing is possible. In the Xilinx Virtex5-LX330T targeted experimental result, integral image memory can be reduced by 50% on a $640{\times}480$ 8-bit gray-scale input image.
Keywords
Integral Image; Image Processing; Image Recognition; Embedded Hardware;
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