• Title/Summary/Keyword: Electronic Hardware

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A Study On Hardware Design for High Speed High Precision Neutron Measurement (고속 고정밀 중성자 측정을 위한 하드웨어 설계에 관한 연구)

  • Jang, Kyeong-Uk;Lee, Joo-Hyun;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.20 no.1
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    • pp.61-67
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    • 2016
  • In this paper, a hardware design method is proposed for high speed high precision neutron radiation measurements. Our system is fabricated to use a high performance A/D Converter for digital data conversion of high precision and high speed analog signals. Using a neutron sensor, incident neutron radiation particles are detected; a precision microcurrent measurement module is also included: this module allows for more precise and rapid neutron radiation measurement design. The high speed high precision neutron measurement hardware system is composed of the neutron sensor, variable high voltage generator, microcurrent precision measurement component, embedded system, and display screen. The neutron sensor detects neutron radiation using high density polyethylene. The variable high voltage generator functions as a 0 ~ 2KV variable high voltage generator that is robust against heat and noise; this generator allows the neutron sensor to perform normally. The microcurrent precision measurement component employs a high performance A/D Converter to precisely and swiftly measure the high precision high speed microcurrent signal from the neutron sensor and to convert this analog signal into a digital one. The embedded system component performs multiple functions including neutron radiation measurement for high speed high precision neutron measurements, variable high voltage generator control, wired and wireless communications control, and data recording. Experiments using the proposed high speed high precision neutron measurement hardware shows that the hardware exhibits superior performance compared to that of conventional equipment with regard to measurement uncertainty, neutron measurement rate, accuracy, and neutron measurement range.

Implementation of 4-Channel Electrolyte Analyzer using ISFET Microsensors (ISFET 마이크로센서를 이용한 4-채널 전해질 분석기의 구현)

  • Bae, S.K.;Kim, K.Y.;Won, C.H.;Cho, B.W.;Kim, C.S.;Sohn, B.K.;Cho, J.H.
    • Proceedings of the KOSOMBE Conference
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    • v.1996 no.05
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    • pp.22-26
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    • 1996
  • In this paper, we designed 4-channel electrolyte analyzer that can measure simultaneousely the 4 electrolytes - pH, $pNa^{+}$, $pCa^{2+}$, and $pK^{+}-$ using 2-point calibration and implemented it. Developed electrolyte analyzer consists of singal processing part, actuator part and control unit for sample flow system. To implement reliable instrument, design considerations are emphasized on flow system and sample chamber that requires small sample volume and prevent air contact with sample solution. In addition to the hardware design, we developed system software which controls full measuring process. After system developed, we verified the system performance by the test measurement for pH, $pNa^{+}$, $pCa^{2+}$, and $pK^{+}$ value.

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Instructions and Data Prefetch Mechanism using Displacement History Buffer (변위 히스토리 버퍼를 이용한 명령어 및 데이터 프리페치 기법)

  • Jeong, Yong Su;Kim, JinHyuk;Cho, Tae Hwan;Choi, SangBang
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.10
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    • pp.82-94
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    • 2015
  • In this paper, we propose hardware prefetch mechanism with an efficient cache replacement policy by giving priority to the trigger block in which a spatial region and producing a spatial region by using the displacement field. It could be taken into account the sequence of the program since a history is based on the trigger block of history record, and it could be quickly prefetching the instructions or data address by adding a stored value to the trigger address and displacement field since a history is stored as a displacement value. Also, we proposed a method of replacing at random by the cache replacement policy from the low priority block when the cache area is full after giving priority to the trigger block. We analyzed using the memory simulator program gem5 and PARSEC benchmark to assess the performance of the hardware prefetcher. As a result, compared to the existing hardware prefecture to generate the spatial region using a bit vector, L1 data cache miss rate was reduced about 44.5% on average and an average of 26.1% of L1 instruction misses occur. In addition, IPC (Instruction Per Cycle) showed an improvement of about 23.7% on average.

Image Resolution Reduction Algorithm of Arbitrary Rate and Its Hardware Architecture (임의의 비율을 지원하는 영상 축소 알고리즘과 하드웨어 구조)

  • Park, Hyun-Sang
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.11
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    • pp.3094-3097
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    • 2009
  • The use of general-purpose divider is inevitable to implement a image down-scaler when an arbitrary scaling ratio is given. To get an output at every clock from the divider, the divider should be implemented by LUT, however, its hardware size will be bigger and bigger as the precision level is increased. In this paper, a new image scaling algorithm is presented for a arbitrary scaling ratio, which do not requires a general-purpose or LUT-based divider. The proposed algorithm utilizes only comparators and adders such that the hardware size can be reduced by 1/10 compared to the conventional approaches.

A Study on a Test Platform for AWS (All-Wheel-Steering) ECU (Electronic Control Unit) of the Bi-modal Tram (저상굴절버스 조향시스템 전자제어장치의 테스트플랫폼 구축에 관한 연구)

  • Lee, Soo-Ho;Moon, Kyeong-Ho;Park, Tae-Won;Kim, Ki-Jung;Choi, Sung-Hun;Kim, Young-Mo
    • Proceedings of the KSR Conference
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    • 2008.06a
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    • pp.1051-1059
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    • 2008
  • In the development process of an ECU (Electrical Control Unit), numerous tests are necessary to evaluate the performance and control algorithm. The vehicle based test is expensive and requires long time. Also, it is difficult to guarantee the safety of the test driver. To overcome the various problems faced in the development process, the ECU test has been done using HIL (Hardware In the Loop). The HIL environment has the actual hardware including an ECU and a virtual vehicle model. In this paper, the test platform environment is devloped for the AWS ECU black box test. The test platform is built on HIL (Hardware In the Loop) architecture. Using the developed test platform, the control algorithm of the AWS ECU can be evaluated under the virtual driving condition of the bi-modal tram. Driving conditions, such as a front steering angle and vehicle velocity, are defined through the PC (Personal Computer) input. Input signals are transformed to electrical signals in the PC. These signals become the input conditions of the AWS ECU. The AWS ECU is stimulated by arbitory input conditons, and responses of the system are observed.

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Safe Adaptive Headlight Controller with Symmetric Angle Sensor Compensator for Functional Safety Requirement (기능 안전성을 위한 대칭형 각도센서 보상기에 기반한 안전한 적응형 전조등 제어기의 설계)

  • Youn, Jiae;Yin, Meng Di;An, Junghyun;Cho, Jeonghun;Park, Daejin
    • IEMEK Journal of Embedded Systems and Applications
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    • v.10 no.5
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    • pp.297-305
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    • 2015
  • AFLS (Adaptive front lighting System) is being applied to improve safety in driving automotive at night. Safe embedded system for controlling head-lamp has to be tightly designed by considering safety requirement of hardware-dependent software, which is embedded in automotive ECU(Electronic Control Unit) hardware under severe environmental noise. In this paper, we propose an adaptive headlight controller with newly-designed symmetric angle sensor compensator, which is integrated with ECU-based adaptive front light system. The proposed system, on which additional backup hardware and emergency control algorithm are integrated, effectively detects abnormal situation and restore safe status of controlling the light-angle in AFLS operations by comparing result in symmetric angle sensor. The controlled angle value is traced into internal memory in runtime and will be continuously compared with the pre-defined lookup table (LUT) with symmetric angle value, which is used in normal operation. The watch-dog concept, which is based on using angle sensor and control-value tracer, enables quick response to restore safe light-controlling state by performing the backup sequence in emergency situation.

Education equipment for FPGA-based multimedia player design (FPGA 기반의 멀티미디어 재생기 설계 교육용 장비)

  • Yu, Yun Seop
    • Journal of Practical Engineering Education
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    • v.6 no.2
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    • pp.91-97
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    • 2014
  • Education equipment for field programmable gate array (FPGA) based multimedia player design is introduced. Using the education equipment, an example of hardware design for color detection and augment reality (AR) game is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs. By controlling audio codec, system-on-chip (SOC) design skills combining a NIOS II soft microprocessor and digital hardware in one FPGA chip are improved. The ability to apply wireless communication and LabView to FPGA-based digital design is also increased.

An Effective Viewport Resolution Scaling Technique to Reduce the Power Consumption in Mobile GPUs

  • Hwang, Imjae;Kwon, Hyuck-Joo;Chang, Ji-Hye;Lim, Yeongkyu;Kim, Cheong Ghil;Park, Woo-Chan
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.8
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    • pp.3918-3934
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    • 2017
  • This paper presents a viewport resolution scaling technique to reduce power consumption in mobile graphic processing units (GPUs). This technique controls the rendering resolution of applications in proportion to the resolution factor. In the mobile environment, it is essential to find an effective resolution factor to achieve low power consumption because both the resolution and power consumption of a GPU are in mutual trade-off. This paper presents a resolution factor that can minimize image quality degradation and gain power reduction. For this purpose, software and hardware viewport resolution scaling techniques are applied in the Android environment. Then, the correlation between image quality and power consumption is analyzed according to the resolution factor by conducting a benchmark analysis in the real commercial environment. Experimental results show that the power consumption decreased by 36.96% on average by the hardware viewport resolution scaling technique.

On the Hardware Complexity of Tree Expansion in MIMO Detection

  • Kong, Byeong Yong;Lee, Youngjoo;Yoo, Hoyoung
    • Journal of Semiconductor Engineering
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    • v.2 no.3
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    • pp.136-141
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    • 2021
  • This paper analyzes the tree expansion for multiple-input multiple-output (MIMO) detection in the viewpoint of hardware implementation. The tree expansion is to calculate path metrics of child nodes performed in every visit to a node while traversing the detection tree. Accordingly, the tree-expansion unit (TEU), which is responsible for such a task, has been an essential component in a MIMO detector. Despite the paramount importance, the analyses on the TEUs in the literature are not thorough enough. Accordingly, we further investigate the hardware complexity of the TEUs to suggest a guideline for selection. In this paper, we focus on a pair of major ways to implement the TEU: 1) a full parallel realization; 2) a transformation of the formulae followed by common subexpression elimination (CSE). For a logical comparison, the numbers of multipliers and adders are first enumerated. To evaluate them in a more practical manner, the TEUs are implemented in a 65-nm CMOS process, and their propagation delays, gate counts, and power consumptions were measured explicitly. Considering the target specification of a MIMO system and the implementation results comprehensively, one can choose which architecture to adopt in realizing a detector.

Scrambler Design and Real Time Implementation for Secure Communication (비화 통신을 위한 바화기 설계 및 실시간 구현)

  • Seok, Gwang-Won;Yeo, Song-Pil;Park, Jung-Ho;Jeong, Jeong-Gyun;Du, Hyeon-Ung;Kim, Seong-Hwan
    • The Journal of the Acoustical Society of Korea
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    • v.15 no.6
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    • pp.41-46
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    • 1996
  • Conversations over telephone line are easily monitored and therefore acceptable level of security is not provided. In this paper, we propose the design of scrambler for secure communication and real time implementation of it. Especially, we con reduce the complexity of hardware and implement it easily by designing the scrambling system which doesn't require synchronization signal, and provide the scrambling filter with a sufficient level of security of adding new gain into the scrambling system.

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