• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.335-343
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• 2024

Real-time target signal processing techniques for FMCW LiDAR are described in this paper. FMCW LiDAR is gaining attention as the next-generation LiDAR for self-driving cars because of its detection robustness even in adverse environmental conditions such as rain, snow and fog etc. in addition to its long range measurement capability. The hardware architecture which is required for high-speed data acquisition, data transfer, and parallel signal processing for frequency-domain signal processing is described in this article. Fourier transformation of the acquired time-domain signal is implemented on FPGA in real time. The paper also details the C-FAR algorithm for ensuring robust target detection from the transformed target spectrum. This paper elaborates on enhancing frequency measurement resolution from the target spectrum and converting them into range and velocity data. The 3D image was generated and displayed using the 2D scanner position and target distance data. Real-time target signal processing and high-resolution image acquisition capability of FMCW LiDAR by using the proposed parallel signal processing algorithms based on FPGA architecture are verified in this paper.

• Journal of IKEEE
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• v.15 no.1
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• pp.76-85
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• 2011

In this paper, we analysed RSS characteristics by external factors and presented an efficient algorithm for real-time location tracking and its hardware system. The proposed algorithm enhanced the ranging accuracy using Kalman Filter based on the RSS DB. The location tracking system that consists of the tag, AP(Access Point), a data collector(Data Receiver) with IEEE 802.15.4(ZigBee) network environment, and location tracking application that reveal locations of each tag is implemented for the test environment. The location tracking system presented in this paper is implemented with MSP430 microprocessor manufactured by TI(Texas Instrument), CC2420 RF chipset and the location tracking application. With the results of the experiment, the proposed algorithm and the system can achieve the efficiency and the accuracy of location tracking with the average error of 19.12cm, and its standard deviation of 5.31cm in outdoor circumstance. Also, the experimental result shows that exact tracking of position in indoor circumstance cannot achieve because of vulnerable RSS with external circumstance.

• The Journal of the Korea Contents Association
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• v.13 no.3
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• pp.141-151
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• 2013

With the spread of Personal Computers(PC) in the 1980's, many people started to deal businesses with PC. From late 1990's, the Internet age with PC have started and many people have showed keen interest in cyber-space and now they are utilizing it. Since 2000's the use of cyber-space have skyrocketed and it caused significant changes to humans' life. There was a huge prosperity to us but the new kind of crime, cyber-crime, was raised. Unlike past physical type of crimes, those cyber-crimes take place in the cyber-space and they have special features of non-facing, anonymity, specialty, technologic, repetition, continuation. Those cyber-crimes are continually growing since 2003 and in 2010 it almost doubled compared to 2003. General cyber-crimes like phishing-scam pornography circulation was most of them and notably perpetrators of them are younger generation. Recently cyber-crimes are showing the trend of advancing more and more and cyber-bullying, fraud like phishing scam are on the rise. The police are responding by making 'Cyber Terror Response Center', but it does not work effectively with the problems of breakup of prevention and investigation unit, procedure of investigation and the system itself. So, I suggest practical use of private security to remedy our police's weakness and to prevent cyber-crimes. Preventing solutions of cyber-crime with private security are physical defense of large-scale servers and vital computers, building of Back-up system to prevent vital data loss, and building of cyber-crime preventing system combining software and hardware.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.21-31
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• 2017

In this paper, the Zynq system-on-chip (SoC) platform is used to design an adaptive noise reduction and edge-detection system using partial reconfiguration. Filters are implemented in a partially reconfigurable (PR) region to provide high computational complexity in real-time, 1080p video processing. In addition, partial reconfiguration enables better utilization of hardware resources in the embedded system from autonomous replacement of filters in the same PR region. The proposed edge-detection system performs adaptive noise reduction if the noise density level in the incoming video sequences exceeds a given threshold value. Results of implementation show that the proposed system improves the accuracy of edge-detection results (14~20 times in Pratt's Figure of Merit) through self-reconfiguration of filter bitstreams triggered by noise density level in the video sequences. In addition, the ZyCAP controller implemented in this paper enables about 2.1 times faster reconfiguration when compared to a PCAP controller.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.61-74
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• 2005

Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

• Journal of IKEEE
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• v.22 no.2
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• pp.495-498
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• 2018

In this paper, we propose an DAP system for dose evaluation of medical and industrial X-ray generator. Based on the DAP measurement technique using the Ion-Chamber, the proposed system can clearly measure the exposure radiation dose generated by the diagnostic X-ray apparatus. The hardware part of the DAP measures the amount of charge in the air that is captured by an X-ray. The high-speed processing algorithm part for cumulative radiation dose measurement through microcurrent measures the amount of charge captured by X-ray at a low implementation cost (power) with no input loss. The wired/wireless transmission/reception protocol part synchronized with the operation of the X-ray generator improves communication speed. The PC-based control program part for interlocking and aging measures the amount of X-ray generated in real time and enables measurement graphs and numerical value monitoring through PC GUI. As a result of evaluating the performance of the proposed system in an accredited testing laboratory, the measured values using DAP increased linearly in each energy band (30, 60, 100, 150 kV). In addition, since the standard deviation of the measured value at the point of 4 division was ${\pm}1.25%$, it was confirmed that the DAP showed uniform measurements regardless of location. It was confirmed that the normal operation was not less than ${\pm}4.2%$ of the international standard.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.37-47
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• 2016

The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.15-25
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• 2012

The research on the FPGA CAD tools in academia has been lacking practicality due to the underlying FPGA fabric architecture which is too simple and inefficient to be applied for commercial FPGAs. Recently, the database of placement positions and routing graphs on commercial FPGA architectures has been built, and provided for enabling the academic development of placement and routing tools. To extend the limit of academic CAD tools even further, we have developed the evaluation toolkit for the K-FPGA architecture which is under development. By providing interface for exchanging data with a commercial FPGA toolkit at every step of mapping, packing, placement and routing in the tool chain, the toolkit enables individual tools to be developed without waiting for the results of the preceding step, and with no dependency on the quality of the results, and compared in detail with commercial tools at any step. Also, the fabric primitive library is developed by extracting the prototype from a reporting file of a commercial FPGA, restructuring it, and modeling the behavior of basic gates. This library can be used as the benchmarking target, and a reference design for new FPGA architectures. Since the architecture is described in a standard HDL which is familiar with hardware designers, and read in the tools rather than hard coded, the tools are "data-driven", and tolerable with the architectural changes due to the design space exploration. The experiments confirm that the developed library is correct, and the functional correctness of applications implemented on the FPGA fabric can be validated by simulation. The placement and routing tools are under development. The completion of the toolkit will enable the development of practical FPGA architectures which, in return, will synergically animate the research on optimization CAD tools.

• Journal of the Korea Society of Computer and Information
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• v.19 no.3
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• pp.63-71
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• 2014

We analyze the execution time of Reed-Solomon coding, which is the MAC-layer forward error correction scheme used in CDMA2000 1xEV-DO broadcast services, under different air channel conditions. The results show that the time constraints of MPEG-4 cannot be guaranteed by Reed-Solomon decoding when the packet loss rate (PLR) is high, due to its long computation time on current hardware. To alleviate this problem, we propose three error control schemes. Our static scheme bypasses Reed-Solomon decoding at the mobile node to satisfy the MPEG-4 time constraint when the PLR exceeds a given boundary. Second, dynamic scheme corrects errors in a best-effort manner within the time constraint, instead of giving up altogether when the PLR is high; this achieves a further quality improvement. The third, video-aware dynamic scheme fixes errors in a similar way to the dynamic scheme, but in a priority-driven manner which makes the video appear smoother. Extensive simulation results show the effectiveness of our schemes compared to the original FEC scheme.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.