• Journal of Power Electronics
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• v.12 no.6
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• pp.947-953
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• 2012

The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.18um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1593-1594
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• 2006

본 논문에서는 모바일 컨버젼스 단말기를 위한 Tunable Image Rejection Filter를 구현 하였다. 이 필터는 TSMC 0.25um 공정을 이용해 시뮬레이션 되었다. 또한 정전기로 인한 소자의 파괴를 방지하기 위해 ESD 패드(Electro Static Discharge Pad)를 추가하였다. 영상 주파수 저지 특성은 WCDMA(2.1GHz), WiBro(2.3GHz), WLAN(2.45) 대역에서 모두 28dB 이상이고, 이때 바이어스 전압은 각각 0.5V, 0.95v, 1.8V의 전압을 가지게 되었다. 삽입 손실은 세 대역에서 모두 2dB 이하이다.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.256-257
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• 2007

정전기방전(Electro-Static Discharge)에 의한 피해는 전기전자제품의 파괴, 분체의 유도성 폭발, 도장 시 화재 등의 산업 각 분야에 걸쳐 인명이나 물질적 형태로 방대하게 발생하고 있다. 본 논문에서는 이와 같은 여러 형태의 ESD 피해형태 중 전기전자제품 관련분야에 대한 국내외적인 동향을 소개하고자 한다. 반도체, 디스플레이, 등 전기전자 산업분야의 소형화, 고속화는 ESD에 대한 민감도를 증가시키고 있으며, 전기전자 환경의 모든 산업분야에서 제품의 생산성, 신뢰성, 안전성에 커다란 영향을 미치고 있다. 그러므로 ESD 관련 국내 산업의 피해실태와 원인, ESD 방지를 위한 국내기술의 수준을 파악하고, 국제적인 기술동향을 분석하는 것은 매우 중요한 일이다. 이를 바탕으로 한 국내 관련 산업의 국제적인 경쟁력 확보를 위한 국가차원의 관리시스템 및 교육제도 도입성의 필요성을 제시하고자 한다.

• Journal of IKEEE
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• v.13 no.1
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• pp.87-93
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• 2009

The paper introduces a silicon controlled rectifier (SCR)-based device with high holding voltage for ESD power clamp. The holding voltage can be increased by extending a p+ cathode to the first n-well and adding second n-well wrapping around n+ cathode. The increase of the holding voltage above the supply voltage enables latch-up immune normal operation. In this study, the proposed device has been simulated using synopsys TCAD simulator for electrical characteristic, temperature characteristic, and ESD robustness. In the simulation result, the proposed device has holding voltage of 3.6V and trigger voltage of 10.5V. And it is confirmed that the device could have holding voltage of above 4V with the size variation of extended p+ cathode and additional n-well.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.9
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• pp.855-860
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• 2016

This study describes the design and implementation of digital Payload power supply. We materialized the interface of the PLDIU and power supply of a satellite bus, and minimized the potential for the occurrence of such erroneous operation circuit ESD through the WCA of the space environment. We designed a reliable power supply through simulation for a TID according to the vibration generated during the launch and space radiation environment, and found no problem in the function and performance through the test space environment after production.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.43-47
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• 2004

We have been using Moisture Barrier Bags for dry packing of semiconductor packages to prevent moisture from absorbing during shipping. Moisture barrier bag material is required to be waterproof, vapor proof and offer superior ESD (Electro-static discharge) and EMI shielding. Also, the bag should be formed easily to the shape of products for vacuum packing while providing excellent puncture resistance and offer very low gas ＆ moisture permeation. There are some problems like pinholes and punctured bags after sealing and before the surface mount process. This failure may easily result in package pop corn crack during board mounting. The bags should be developed to meet the requirements of excellent electrical and physical properties by means of optimization of their raw material composition and their thickness. This study investigates the performance of moisture barrier bags by characterization of their mechanical endurance, tensile strength and through thermal analysis. By this study, we arrived at a robust material composition (polyester/Aluminate) for better packing.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1673-1681
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• 2015

A low dropout (LDO) regulator with a wide-bandwidth is proposed in this paper. The regulator features a Human Body Model (HBM) 8kV-class high robustness ElectroStatic Discharge (ESD) protection circuit, and two error amplifiers (one with low gain and wide bandwidth, and the other with high gain and narrow bandwidth). The dual error amplifiers are located within the feedback loop of the LDO regulator, and they selectively amplify the signal according to its ripples. The proposed LDO regulator is more efficient in its regulation process because of its selective amplification according to frequency and bandwidth. Furthermore, the proposed regulator has the same gain as a conventional LDO at 62 dB with a 130 kHz-wide bandwidth, which is approximately 3.5 times that of a conventional LDO. The proposed device presents a fast response with improved load and line regulation characteristics. In addition, to prevent an increase in the area of the circuit, a body-driven fabrication technique was used for the error amplifier and the pass transistor. The proposed LDO regulator has an input voltage range of 2.5 V to 4.5 V, and it provides a load current of 100 mA in an output voltage range of 1.2 V to 4.1 V. In addition, to prevent damage in the Integrated Circuit (IC) as a result of static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class (Chip level) ESD protection circuit of a P-substrate-Triggered Silicon Controlled Rectifier (PTSCR) type with high robustness characteristics.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.54-60
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• 2007

In this study novel ESD protection device, namely, N/P-type Low Voltage Triggered SCR, has been proposed, for high speed I/O interface. Proposed device could lower high trigger voltage($\sim$20V) of conventional SCR and reduce latch-up phenomenon of protection device during the normal condition. In this Study, the proposed NPLVTSCR has been simulated using TMA MEDICI device simulator for electrical characteristic. Also the proposed device's test pattern was fabricated using 90nm TSMC's CMOS process and was measured electrical characteristic and robustness. In the result, NPLVTSCR has 3.2V $\sim$ 7.5V trigger voltage and 2.3V $\sim$ 3.2V holding voltage by changing PMOS gate length and it has about 2kV, 7.5A HBM ESD robustness(IEC61000-4-2).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.979-986
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• 2013

In this paper, a TVS diode which is commonly used as a ESD protector in wireless communication devices could cause antenna wireless sensitivity to decrease has been analyzed. When a smartphone doesn't have enough space to place many components, there would be its speaker near antenna area. In order to protect ESD coming through the speaker there also could be a TVS within antenna GND area. Digital audio signal which was sent to speaker and CDMA RF communication signal coupled from antenna was mixed by TVS. And this leakage current running through TVS resulted in decrease of antenna wireless sensitivity. The results of various experiments can be explained using circuit simulation. Following works will give us some insights that can reduce unwanted summation of digital and RF signal due to nonlinearity of ESD protectors.