• 전기학회논문지
• /
• 제65권5호
• /
• pp.873-877
• /
• 2016

This paper proposed the structure that applied superconductors to the neutral line of a transformer and applied the normal conductors to the third line. The superconductor applied to the neutral line of a transformer limited the peak value of initial fault current, while the normal conductor finally limited the fault current. In order to secure the operating reliability of transformer type Superconducting Fault Current Limiter (SFCL) of previously proposed structure, we analyzed the operating characteristics according to the fault types. We tested a line-to-ground fault and a line-to-line fault. As a result of the experiment, all the faults showed that the superconductor stably limited the peak-value of initial fault current. Also, the normal conductor finally limited the fault current. Based on this research results, We thought that if the structure of inserting superconductor into the neutral line is applied to the real system, it could improve the reliability and stability of the power system.

• Journal of Electrical Engineering and Technology
• /
• 제7권6호
• /
• pp.859-868
• /
• 2012

A new fault location algorithm based on stationary wavelet transform and its verification experiment results are described for HVDC submarine cables in this paper. For wavelet based fault location algorithm, firstly, 4th level approximation coefficients decomposed by wavelet transform function are superimposed by correlation, then the distance to the fault point is calculated by time delay between the first incident signal and the second reflected signal. For the verification of this algorithm, the real experiments based on various fault conditions and return types of fault current are performed at HVDC submarine cable test yard located in KEPCO(Korea Electric Power Corporation) Power Testing Center of South Korea. It proves that the fault location method proposed in this paper is very simple but very quick and accurate for HVDC submarine cable fault location.

• 한국전기전자재료학회논문지
• /
• 제36권6호
• /
• pp.614-619
• /
• 2023

The fault current limiting characteristics of three-phase transformer type superconducting fault current limiter (SFCL), which consisted of three-phase primary and secondary windings wound on E-I iron core, one high-TC superconducting (HTSC) element connected with the secondary winding of one phase and another HTSC element connected in parallel with other two secondary windings of two phases, were analyzed. Unlike other three-phase transformer type SFCLs with three HTSC elements, three-phase transformer type SFCL using double quench has the merit to perform fault current limiting operation for three-phase ground faults with two HTSC elements. To verify its proper three-phase ground fault current limiting operation, three-phase ground faults such as single-line ground, double-line ground and triple-line ground faults were generated in three-phase simulated power system installed with three-phase transformer type SFCL using double quench. From analysis of its fault current limiting characteristics based on tested results, three-phase transformer type SFCL using double quench was shown to be effectively operated for all three-phase ground faults.

• 한국전기전자재료학회논문지
• /
• 제18권9호
• /
• pp.851-855
• /
• 2005

We investigated the unbalanced characteristics of the superconducting fault current limiters (SFCLs) based on YBCO thin films with a single line-to-ground fault. When a single line-to-ground fault occurred, the short circuit current of a fault phase increased about 6 times of transport currents after the fault onset but was effectively limited to the designed current level within 2 ms by the resistance development of the SFCL. The fault currents of the sound phases almost did not change because of their direct grounding system. The unbalanced rates of a fault phase were distributed from 6.4 to 1.4. It was found that the unbalanced rates of currents were noticeably improved within one cycle after the fault onset. We calculated the zero phase currents for a single line-to-ground fault using the balanced component analysis. The positive sequence resistance was reduced remarkably right after the fault onset but eventually approached the balanced positive resistance component prior to the system fault. This means that the system reaches almost the three-phase balanced state in about 60 ms after the fault onset at the three-phase system.

• 전기학회논문지
• /
• 제61권11호
• /
• pp.1752-1757
• /
• 2012

With the development in industry, power demand has increased rapidly. As consumption of power has increased, Demand for new power line and electric capacity has risen. However, in the event of fault, problems occur in extending the range of fault coverage and increasing fault current. In these reasons, protection devise is recognized as the prevention of an accident and fault current. This paper dealt with minimizing fault propagation and limiting fault current by adjusting fault current limiter (FCL) with fast interrupter. At this point, we compared and analyzed characteristics between non-inductive resistance and fault current which is limited by superconducting units. In normal state of the power system, power was supplied to the load, but when fault occurred, the interrupter was operated as CT which detected the over-current. Its operation made the limitation of fault current through a FCL. We concluded that the limiter using superconducting units was more efficient with the increase of power voltage. Superconducting fault current limiter with the fast interrupter prevented the spread of a fault, and improved reliability of power system.

• 대한전기학회논문지:전력기술부문A
• /
• 제51권8호
• /
• pp.371-378
• /
• 2002

This paper presents the rapid and accurate algorithm for fault detection and location estimation in the transmission line. This algorithm uses wavelet transform for fault detection and harmonics elimination and utilizes least square error method for fault impedance estimation. Wavelet transform decomposes fault signals into high frequence component Dl and low frequence component A3. The former is used for fault phase detection and fault types classification and the latter is used for harmonics elimination. After fault detection, an adaptive data window technique using LSE estimates fault impedance. It can find a optimal data window length and estimate fault impedance rapidly, because it changes the length according to the fault disturbance. To prove the performance of the algorithm, the authors test relaying signals obtained from EMTP simulation. Test results show that the proposed algorithm estimates fault location within a half cycle after fault irrelevant to fault types and various fault conditions.

• 한국조명전기설비학회:학술대회논문집
• /
• 한국조명전기설비학회 2003년도 학술대회논문집
• /
• pp.279-281
• /
• 2003

We analysed the operating properties of resistive type superconducting fault current limiters (SFCLs) based on YBCO thin films with a single line-to-ground fault. When a single line-to-ground fault occurred, the short circuit current of a fault phase increased up to about 6 times of transport currents immediately after the fault instant and was effectively limited to the designed current level within 2 ms by the resistance development of the SFCL. The fault currents of the sound phases almost did not change because of their direct grounding system. The unsymmetrical rates of a fault phase were distributed from 6.4 to 1.4. It was found that the unsymmetrical rates of currents were noticeably improved within one cycle after the fault instant. We calculated the zero phase currents for a single line-to-ground fault using the symmetrical component analysis. The positive sequence resistance was reduced remarkably right after the fault but eventually approached the balanced positive resistance component prior to the system fault. This means that the system reaches almost the three-phase symmetrical state in about 60 ㎳ after the fault. The ground currents were almost 3 times of the zero phase mts since most of the fault currents flowed through the grounding line.

• KEPCO Journal on Electric Power and Energy
• /
• 제6권2호
• /
• pp.119-122
• /
• 2020

With recent ESS (Energy Storage System) fire accident, the fault protection performance is becoming more important. However, there has never been any experiments with the protection performance on the faults in the ESS system level. In this study, the effect of AC ground fault and IGBT (Insulated Gate Bipolar mode Transistor) short-circuit failure on MW class ESS was performed experimentally for the first time in the world. First of all, the effect of the AC single line ground fault on battery was analyzed. Moreover, the transient voltage was investigated as a function of the battery capacity and the power level. Finally, the breaking capability and insulation performance of ESS were examined under PCS short-circuit fault condition. Through the tests, it was found that ESS protection system safely blocked the faulty current regardless of the faults, whereas the electronic parts such as IGBT and MC (Magnetic Contactor) were broken by the fault current. Also, the electrical breakdown in ESS resulted from the transient voltage during the protection process.

• Journal of Power Electronics
• /
• 제14권4호
• /
• pp.695-703
• /
• 2014

In this paper, a fault detection scheme for DC-link voltage sensor and its fault tolerant control strategy for three-phase AC/DC/AC PWM converters are proposed, where the Luenberger observer is applied to estimate the DC-link voltage. The Luenberger observer is based on a converter model, which is derived from the voltage equations of a grid-side converter and the power balance on a DC link. A fault of the voltage sensor is detected by comparing the measured value of the DC-link voltage with the estimated one. When a sensor fault is detected, a fault tolerant control strategy is performed, where the estimated DC-link voltage is used for the feedback control. The estimation error from the observer is about 1.5 V, which is sufficiently accurate for feedback control. In addition, it is shown that the observer performance is robust to parameter variations of the converter. The validity of the proposed method has been verified by simulation and experimental results.

• 전기학회논문지
• /
• 제64권5호
• /
• pp.718-725
• /
• 2015

This paper proposes a novel level-shifted PWM (LS-PWM) strategy for fault tolerant cascaded multilevel inverter. Most proposed fault-tolerant operation methods in many of studies are based on a phase-shifted PWM (PS-PWM) method. To apply these methods to multilevel inverter systems using LS-PWM, two additional steps will be implemented. During the occurrence of a single-inverter-cell fault, the carrier bands scheme is reconfigured and modulation levels of inverter cells are reassigned in this proposed fault-tolerant operation. The proposed strategy performs balanced three-phase line-to-line voltages and line currents when a switching device fault occurs in a cascaded multilevel inverter using LS-PWM. Simulation and experimental results are included in the paper to verify the proposed method.