• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.90-100
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• 2011

We present a parallel bi-conjugate gradient (Bi-CG) matrix solver for large scale Bio-FET simulations based on recent graphics processing units (GPUs) which can realize a large-scale parallel processing with very low cost. The proposed method is focused on solving the Poisson equation in a parallel way, which requires massive computational resources in not only semiconductor simulation, but also other various fields including computational fluid dynamics and heat transfer simulations. As a result, our solver is around 30 times faster than those with traditional methods based on single core CPU systems in solving the Possion equation in a 3D FDM (Finite Difference Method) scheme. The proposed method is implemented and tested based on NVIDIA's CUDA (Compute Unified Device Architecture) environment which enables general purpose parallel processing in GPUs. Unlike other similar GPU-based approaches which apply usually 32-bit single-precision floating point arithmetics, we use 64-bit double-precision operations for better convergence. Applications on the CUDA platform are rather easy to implement but very hard to get optimized performances. In this regard, we also discuss the optimization strategy of the proposed method.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.45-52
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• 2008

We investigated the design of an RF-powered, wireless temperature sensor tag chip using $0.18-{\mu}m$ CMOS technology. The transponder generates its own power supply from small incident RF signal using Schottky diodes in voltage multiplier. Ambient temperature is measured using a new low-power temperature-to-voltage converter, and an 8-bit single-slope ADC converts the measured voltage to digital data. ASK demodulator and digital control are combined to identify unique transponder (ID) sent by base station for multi-transponder applications. The measurement of the temperature sensor tag chip showed a resolution of $0.64^{\circ}C/LSB$ in the range from $20^{\circ}C$ to $100^{\circ}C$, which is suitable for environmental temperature monitoring. The chip size is $1.1{\times}0.34mm^2$, and operates at clock frequency of 100 kHz while consuming $64{\mu}W$ power. The temperature sensor required a -11 dBm RF input power, supported a conversion rate of 12.5 k-samples/sec, and a maximum error of $0.5^{\circ}C$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.34-39
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• 2016

A low-voltage, low-power analog front-end IC for neural recording implant devices is presented. The proposed IC consists of a low-noise neural amplifier and a programmable active bandpass filter to process neural signals residing in the band of 1 Hz to 5 kHz. The neural amplifier is based on a source-degenerated folded-cascode operational transconductance amplifier (OTA) for good noise performance while the following bandpass filter utilizes a low-power current-mirror based OTA with programmable high-pass cutoff frequencies from 1 Hz to 300 Hz and low-pass cutoff frequencies from 300 Hz to 8 kHz. The total recording analog front-end provides 53.1 dB of voltage gain, $4.68{\mu}Vrms$ of integrated input referred noise within 1 Hz to 10 kHz, and noise efficiency factor of 3.67. The IC is designed using $18-{\mu}m$ CMOS process and consumes a total of $3.2{\mu}W$ at 1-V supply voltage. The layout area of the IC is $0.19 mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.136-143
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• 2013

In this paper, a algorithm to find joints of a small animal like a lizard from the multiple-view silhouette images is presented. The proposed algorithm is able to calculate the 3D coordinates so that the locomotion of the lizard is markerlessly reconstructed. The silhouette images of the lizard was obtained by a adaptive threshold algorithm. The skeleton image of the silhouette image was obtained by Zhang-Suen method. The back-bone line, head and tail point were detected with the A* search algorithm and the elimination of the ortho-diagonal connection algorithm. Shoulder joints and hip joints of a lizard were found by $3{\times}3$ masking of the thicked back-bone line. Foot points were obtained by morphology calculation. Finally elbow and knee joint were calculated by the ortho distance from the lines of foot points and shoulder/hip joint. The performance of the suggested algorithm was evaluated through the experiment of detecting joints of a small lizard.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.9-15
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• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.

• Journal of IKEEE
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• v.14 no.1
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• pp.25-32
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• 2010

In this paper, we analyze the location accuracy of real-time locating systems (RTLS) in multipath environments, where the RTLS complies with an ISO/IEC 24730-2 international standard. RTLS readers should have an ability not only to recover the transmitted signal but also provide arrival timing information from the received signal. In the multipath environments, in general, the transmitted signal goes through both direct and indirect paths, and then it becomes some distorted form of the transmitted signal. Such multipath components have a critical effect on deciding the first arrival timing of the received signal. To analyze the location error of the RTLS in the multipath environments, we assume two multipath components without considering an additive white Gaussian noise. Through the simulation and real test results, we confirm that the location error does not occur when the time difference between two paths is more than 1.125Tc, but the location error of about 2.4m happens in case of less than 0.5Tc. In particular, we see that the resolvability of two different paths depends largely on the phase difference for the time difference of less than 1Tc.

• Journal of IKEEE
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• v.18 no.4
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• pp.593-602
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• 2014

One of the purposes of an artificial neural netowrk(ANNet) is to implement the largest number of functions as possible with the smallest number of nodes and layers. This paper presents a CoreNet which has a multi-leveled input value and a multi-leveled output value with a 2-layered ANNet, which is the basic structure of an ANNet. I have suggested an equation for calculating the capacity of the CoreNet, which has a p-leveled input and a q-leveled output, as $a_{p,q}={\frac{1}{2}}p(p-1)q^2-{\frac{1}{2}}(p-2)(3p-1)q+(p-1)(p-2)$. I've applied this CoreNet into the simulation model 1(5)-1(6), which has 5 levels of an input and 6 levels of an output with no hidden layers. The simulation result of this model gives, the maximum 219 convergences for the number of implementable functions using the cot(${\sqrt{x}}$) input leveling method. I have also shown that, the 27 functions are implementable by the calculation of weight values(w, ${\theta}$) with the multi-threshold lines in the weight space, which are diverged in the simulation results. Therefore the 246 functions are implementable in the 1(5)-1(6) model, and this coincides with the value from the above eqution $a_{5,6}(=246)$. I also show the implementable function numbering method in the weight space.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.11
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• pp.1271-1276
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• 2015

The recent trend is that diesel power generation on islands where its prime cost for power generation is high is replaced by new and renewable energy. Therefore, south Jeolla province is progressing the construction project of self-sufficient islands for the areas where power is supplied by depending on diesel generators, which is the project that power is supplied through eco-friendly energy source using sunlight, wind power and energy storage device etc. However, it is difficult to construct new and renewable energy source with the capacity to respond to the load perfectly due to its environmental and geographical conditions regarding capacity design of new and renewable energy. Besides, Microgrid design considering appropriate capacity design of the system components and efficient operation is required through the analysis of climate conditions and load patterns from the design stage for optimal composition of a hybrid system with economic feasibility. Therefore, this study is aimed to conduct a research on optimal combination, capacity calculation and economic feasibility by comprising a hybrid power generation system which will replace 40% of power generation by diesel as new and renewable energy source for Geomun Island where has more than 300 households and requires expansion of the facility among islands located in southwest coast.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1098-1099
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• 2015

${\bullet}$ 시험대상: 영월태양광 4,990kW(998kW ${\times}$ 5호) ${\bullet}$ 13.07.31 연계기술검토의뢰 ${\bullet}$ 13.08.28 한전검토결과: 인근변전소 영월S/S(40MW) 초과로 10.8km 지점의 평창 D/L 평창간 347호 주진S/S에 다음의 보완대책과 연계 권고 ${\cdot}$ 문제점: 적정전압이탈 및 순시전압변동률 유지불가 ${\cdot}$ 연계기준만족을 위해 한전에서 제시한 보완대책 : 계통용량증설(설비보강), 연계용량 감소 및 전용선로 연계 ${\bullet}$ 14.01.09 분산형설치자의 용역사(에이스기술단)에서 송배전용전기설비 이용규정과 연계기준 만족을 위한 보완대책 제안 ${\cdot}$ 태양광발전시스템 인버터 자동전압(역률/무효전력) 조정기능 및 감시설비 구비 ${\cdot}$ 최적 공통연결점 선정: 분산형전원으로 부터 전기적으로 가장 가까운 영월D/L 영월S/S측에 개폐장치설치 하고 주진S/S 측으로 연계 ${\bullet}$ 14.01.29~06.19 한전(전력연구원)의 유효성 검토 ${\cdot}$ 보완대책 기술적 유효(실증시험 시행 후 시행공문 발송 예정) ${\bullet}$ 14.08.08 송배전용전기설비 이용규정 개정에 따른 협의 ${\cdot}$ 변압기 대당 20MW에서 25MW ${\cdot}$ 변전소 전체 60MW에서 75MW까지 허용 ${\cdot}$ 영월 S/S 측 문곡/영월 D/L 연계 공사 협의 ${\bullet}$ 14.10.04 사용전검사, 한전계통연계운전 시작 ${\bullet}$ 인버터 고정역률(99.9~100%) 운전 시험 ${\cdot}$ 14.11.21 22.9kV 계전기(SEL-751) 5대, 15분 간격 자료저장 ${\cdot}$ SEL-751/USB to RS232C/노트북 15분간격 측정(첨부) ${\bullet}$ 14.03.07 인버터 역률 95.0% 조정 15분간격 측정(첨부) ${\bullet}$ 변압기탭 선정과 인버터전압조정협조시험 계획 ${\cdot}$ 변압기탭을 현장에서 상하 1탭씩 변경 ${\cdot}$ 인버터역률을 인버터공급사에서 원격조정 ${\cdot}$ 22.9kV 보호계전기 SEL-751, 15분 간격 측정 ${\cdot}$ 인버터 370V 계전기 K-PAM DG3000/현장감시설비 연계 ${\cdot}$ 15분 간격 측정 저장 ${\cdot}$ 현장감시설비/인터넷 연결 원격측정(첨부예정)