• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.5
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• pp.76-79
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• 2011

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.4
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• pp.59-62
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• 2011

• Korean Journal of Materials Research
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• v.20 no.6
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• pp.319-325
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• 2010

3-D IC integration enables the smallest form factor and highest performance due to the shortest and most plentiful interconnects between chips. Direct metal bonding has several advantages over the solder-based bonding, including lower electrical resistivity, better electromigration resistance and more reduced interconnect RC delay, while high process temperature is one of the major bottlenecks of metal direct bonding because it can negatively influence device reliability and manufacturing yield. We performed quantitative analyses of the interfacial properties of Al-Al bonds with varying process parameters, bonding temperature, bonding time, and bonding environment. A 4-point bending method was used to measure the interfacial adhesion energy. The quantitative interfacial adhesion energy measured by a 4-point bending test shows 1.33, 2.25, and $6.44\;J/m^2$ for 400, 450, and $500^{\circ}C$, respectively, in a $N_2$ atmosphere. Increasing the bonding time from 1 to 4 hrs enhanced the interfacial fracture toughness while the effects of forming gas were negligible, which were correlated to the bonding interface analysis results. XPS depth analysis results on the delaminated interfaces showed that the relative area fraction of aluminum oxide to the pure aluminum phase near the bonding surfaces match well the variations of interfacial adhesion energies with bonding process conditions.

• Journal of Sensor Science and Technology
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• v.20 no.1
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• pp.58-63
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• 2011

A low loss radio frequency(RF) micro electro mechanical systems(MEMS) switch driven by a low actuation voltage was designed for the development of a new RF MEMS switch. The RF MEMS switch should be encapsulated. The glass cap and fabricated RF MEMS switch were assembled by the Au/Sn eutectic bonding principle for wafer-level packaging. The through-vias on the glass substrate was made by the glass dry etching and Au electroplating process. The packaged RF MEMS switch had an actuation voltage of 12.5 V, an insertion loss below 0.25 dB, a return loss above 16.6 dB, and an isolation value above 41.4 dB at 6 GHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.262-263
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• 2005

For mechanical and electrical stability and environment protection, Cu and stainless steel stabilizer is laminated to Ag layer to produce a composite neutral-axis(N-A) architecture in which the YBCO layer is centered between the oxide buffered metallic substrate and stabilizer strip lamination. this architecture allows the wire to meet operational requirements including stresses at cryogenic temperature, winding tensions, mechanical bending requirements thermal and electrical stability under fault conditions. we have experimentally studied mechanical properties of laminated stainless steel stabilizer on YBCO coated conductors. we have laminated YBCO coated conductors by continuous dipping soldering process. we have investigated lamination interface between solder and stabilizer, YBCO coated conductor. we evaluated bonding properties tensile / shear bonding strength, peeling strength laminated YBCO coated conductors.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.181-184
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• 2017

Multilayer ceramics in which piezoelectric layers of $0.90Pb(Zr_{0.48}Ti_{0.52})O_3-0.05Pb(Mn_{1/3}Sb_{2/3})O_3-0.05Pb(Zn_{1/3}Nb_{2/3})O_3$ (0.90PZT-0.05PMS-0.05PZN) stack alternately with silver electrode layers were prepared by an advanced low-temperature co-fired ceramic (LTCC) method. The electrical properties and bonding strength of the multilayers were associated with the interface morphologies between the piezoelectric and silver-electrode layers. Usually, the inner silver electrodes are fabricated by sintering silver paste in multi-layer stacks. To improve the interface bonding strength, piezoelectric powders of 0.90PZT-0.05PMS-0.05PZN with an average particle size of $23{\mu}m$ were added to silver paste to form a gradient interface. SEM observation indicated clear interfaces in multilayer ceramics without powder addition. With the increase of piezoelectric powder addition in the silver paste, gradient interfaces were successfully obtained. The multilayer ceramics with gradient interfaces present greater bonding strength as well as excellent piezoelectric properties for 30~40 wt% of added powder. On the other hand, over addition greatly increased the resistance of the inner silver electrodes, leading to a piezoelectric behavior like that of bulk ceramics in multilayers.

• Journal of the Semiconductor & Display Technology
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• v.3 no.3
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• pp.5-9
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• 2004

A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.

• Journal of the Korean institute of surface engineering
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• v.54 no.5
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• pp.207-212
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• 2021

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 ℃, 150 ℃, 200 ℃, 350 ℃ and the pressure of 2303 N/cm² and 3087 N/cm². At 2303 N/cm², the good bonding of copper substrate was confirmed at 350 ℃, and at the increased pressure of 3087 N/cm², the bonding condition of Cu was confirmed at low temperature junction temperature of 200 ℃. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm² and diffusion of Cu atoms at high temperature of 350 ℃, which can lead to degradation in semiconductor manufacturing.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.417-418
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• 2008

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.132.1-132.1
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• 2007