• ETRI Journal
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• v.41 no.6
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• pp.863-872
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• 2019

Elliptic curve cryptography is a relatively lightweight public-key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low-end IoT processors (ie, 8-bit AVR and 16-bit MSP processors). In particular, the three-level and two-level subtractive Karatsuba algorithms are adopted for multi-precision multiplication on AVR and MSP processors, respectively, and two-level Karatsuba routines are employed for multi-precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat-based inversion operations are used to mitigate side-channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.188-198
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• 1994

The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.3
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• pp.263-269
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• 1999

In this paper, an unifying design algorithm is presented for efficient digital implementation of continuous PID controller using general discrete orthogonal functions. The proposed algorithm is an algebraic method to determine controller parameters, which can unify controller design procedures divided into three ways. A set of linear equations for the controller design are derived from simple algebraic transformation based on general discrete orthogonal functions. By solving these equations, all of the controller parameters can be determined directly and simultaneously, which thus makes the design procedure systematic and straightforward. It does not involve any trial and error procedure, hence the difficulty of conventional approach can be avoided. The simulation results and discussions are given to demonstrate the efficiency of the proposed method.

• Journal of the Korean Society of Systems Engineering
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• v.6 no.2
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• pp.7-14
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• 2010

Systematic and efficient Management of Development requirements will lead to success of project such as aircraft system development consisting of complex subsystem. For such reason, Requirements management tools have been used in most of project. In the case of FA-50 development project, requirements management tools have been used for systematic and efficient management of FA-50 Requirements. Especially FA-50 system was designed on the basis of the TA-50 configuration. Therefore, it needs traceability of requirements about functions, which have been already developed and will be newly developed. This paper was described about the implementation method of FA-50 development requirements traceability management.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1997.10a
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• pp.52-55
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• 1997

In this paper, both the generalization of one artificial variable technique to the general bound problem and the efficient implementation of the technique are suggested. When the steepest-edge method is used as a pricing rule in the simplex method, it is easy to update the reduced cost and the simplex multiplier every iteration. Therefore, one artificial variable technique is more efficient than Wolfe's method in which the reduced cost and simplex multiplier must be recalculated in every iteration. When implementing the one artificial variable technique on the LP problems with the general bound restraints on the variables, an arbitrary basic solution which satisfies the bound restraints is sought first, and the artificial column which adjusts the infeasibility is introduced. The phase one of the simplex method minimizes the one artificial variable. The efficient implementation technique includes the splitting, scaling, storage of the artificial column, and the cure of infeasibility problem.

• Journal of the Korean Operations Research and Management Science Society
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• v.21 no.3
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• pp.63-74
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• 1996

Ordering plays an important role in solving an LP problem with sparse matrix by the interior point method. Since ordering is NP-complete, we try to find an efficient method. The objective of this paper is to present an efficient heuristic ordering method for implementation of the minimum deficiency method. Both the ordering method and the data structure play important roles in implementation. First we define a new heuristic pseudo-deficiency ordering method and a data structure for the method-quotient graph and cliqued storage. Next we show an experimental result in terms of time and nonzero numbers by NETLIB problems.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.2
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• pp.51-58
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• 2014

As WSNs(Wireless Sensor Networks) are being deployed widely in diverse application areas, their management and maintenance become more important. Recent sensor node software takes modular software architectures in pursuit of flexible software management and energy efficient reprogramming. To realize an flexible and efficient modular architecture particularly on resource constrained mote-class sensor nodes that are implemented with MCUs(Micro-Controller Units) of a single address space. an appropriate module linking model is essential to resolve and bind the inter-module global symbols. This paper identifies a design space of module linking model and respectively their implementation frameworks. We then establish a taxonomy for module linking models by exploring the design space of module linking models. Finally, we suggest an implementation framework respectively for each module linking model in the taxonomy. We expect that this work lays the foundations for systematic innovation toward more flexible and efficient modular software architectures for WSNs.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.12
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• pp.27-34
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• 1994

Block matching motion estimation is the most widely used method for motion compensated coding of image sequences. Based on a two dimensional systolic array, VLSI architecture and implementation of the full search block matching algorithm are described in this paper. The proposed architecture improves conventional array architecture by designing efficient processing elements that can control the data prodeuced by efficient search window division method. The advantages are that 1) it allows serial input to reduce pin counts for efficient composition of local memories but performs parallel processing. 2) It is flexible and can adjust to dimensional changes of search windows with simple control logic. 3) It has no idel time during the operation. 4) It can operate in real/time for low and main level in MPEG-2 standard. 5) It has modular and regular structure and thus is sutiable for VLSI implementation.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.12-16
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• 2013

Sensor network is one of the strongest technologies for various applications including home automation, surveillance system and monitoring system. To ensure secure and robust network communication between sensor nodes, plain-text should be encrypted using encryption methods. However due to their limited computation power and storage, it is difficult to implement public key cryptography, including elliptic curve cryptography, RSA and pairing cryptography, on sensor networks. However, recent works have shown the possibility that public key cryptography could be made available in a sensor network environment by introducing the efficient multi-precision multiplication method. The previous method suggested a broad rule of multiplication to enhance performance. However, various features of sensor motes have not been considered. For optimized implementation, unique features should be handled. In this paper, we propose a fully optimized multiplication method depending on a different specification for sensor motes. The method improves performance by using more efficient instructions and general purpose registers.