• Title/Summary/Keyword: EPC Class-1 Generation

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Implementation of UHF RFID Tag Emulator (UHF 대역의 RFID 태그 에뮬레이터 구현)

  • Park, Kyung-Chang;Kim, Hanbyeori;Lee, Sang-Jin;Kim, Seung-Youl;Park, Rae-Hyeon;Kim, Yong-Dae;You, Young-Gap
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.11
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    • pp.12-17
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    • 2009
  • This paper presents a tag emulator for a UHF band RFID system. The tag emulator supports the 1800-6C and EPC global class 1 generation 2 standards. The transmitted signal from a reader is generated using the PIE coding and ASK modulation methods. Signals of a tag are from the FM0 coding and ASK modulation methods. The ARM7 processor carries out the overall control of the system and signal analysis of incoming data. The verification of the tag emulator employs the application platform implemented in C++. Users can define parameter values for protocol during the application run. The tag emulator presented in this paper allows evaluating various design alternatives of the target RFID system in real applications.

Implementation of Digital CODEC for RFID Dual-band Reader system (RFID Dual-band 리더 시스템의 디지털 코덱 설계)

  • Sim, Jae-Hee;Lee, Yong-Joo;Lee, Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.10A
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    • pp.1015-1022
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    • 2007
  • In this paper, dual-band digital codec for UHF(Ultra High Frequency) and MW(Micro Wave) is proposed for an RFID reader system. Most RFID systems have been supported only one protocol. But, There are many protocols of each bandwidth. Especially, UHF bandwidth which is widely used on the globe consists of A,B,C type, and more standards will be established. Recently, Since an interest about mobile RFID system is increasing, the RFID system with more than one protocol will be need. Therefore, this paper suggests a dual-band digital codec with UHF and MW bands for an RFID reader system. Standards used in this system are 18000-6C and 18000-4 standards. The digital codec is synthesize by the Quartus II compiler. Target device is EPC20Q240C8 which is family of CycloneII. Main Clock is 19.2MHz and elements of FPGA which is used for the system is 18,752.

Design of a Frequency Synthesizer for UHF RFID Reader Application (UHF 대역 RFID 리더 응용을 위한 주파수합성기 설계)

  • Kim, K.H.;Oh, K.C.;Park, D.S.;Yu, C.G.
    • Proceedings of the KIEE Conference
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    • 2007.10a
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    • pp.191-192
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    • 2007
  • This paper presents a 900MHz fractional-N frequency synthesizer for radio frequency identification (RFID) reader using $0.18{\mu}m$ standard CMOS process. The IC meets the EPC Class-1 Generation-2 and ISO-18000 Type-C standards. To minimize VCO pulling, the 900MHz VCO is generated by a 1.8GHz VCO followed by a frequency divider. The settling time of the synthesizer is less than $20{\mu}m$. The frequency synthesizer achieves the phase noise of -105.6dBc/Hz at 200kHz offset. The frequency synthesizer occupies an area of $1.8{\times}0.99mm^2$, and dissipates 8mA from a low supply voltage of 1.8V.

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Design and Implementation of System in Package for a HF/UHF Multi-band RFID Reader (HF/UHF 멀티밴드 RFID 리더의 SiP 설계 및 구현)

  • An, Kwang-Dek;Yi, Kyeong-Il;Kim, Ji-Gon;Cho, Jung-Hyun;Kim, Shi-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.10
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    • pp.59-65
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    • 2008
  • We have proposed a UHF/HF multi-band RFID reader, and have implemented it into a system in a package(SiP). The proposed SiP RFID reader has been designed to support both for EPCgloabal Class1 Generation2 protocol of UHF band, and 13.56MHz RFID protocols of ISO14443 A/B type, and ISO15693 standards. The operating mode is controlled by embedded RISC core, and the mode can be selected by users. The area of implemented SiP is $40mm{\times}40mm$ with 4 metal layers. The implemented reader SiP operates at single supply voltage of 3.3V. The maximum current consumption is 210mA. The operating distances are 5cm for 13.56MHz modes, and 20cm for UHF mode.