• 반도체디스플레이기술학회지
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• 제8권4호
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• pp.77-82
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• 2009

In robot operation, a motor with multi-degree of freedom motion control and an encoder for motor control are needed. To perform precise motion, location, and velocity control, the operation of motor and encoder with superior performance is important. In this paper, we studied performance evaluation system that can evaluate the performance of motor and encoder. The performance of motor and encoder can be evaluated in terms of disconnection check, signal variation count, and U, V, W signal check. Disconnection check verifies signal connection between a motor and an encoder, signal variation check verifies A, B signal by counting the number of signal A, B when a motor revolves, and U, V, W signal check verifies operating direction of a motor. The result is shown at graphic LCD integrated in system, and can be checked in PC with PC communication.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.100-103
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• 2008

본 논문에서는 AMBA 기반으로 사용될 수 있는 H.264용 Encoder Hardware 모듈(Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, Motion Estimation)을 Integration하여 설계하였다. 설계된 모듈은 한 매크로 블록당 최대 440 cycle내에 동작한다. 제안된 Encoder 구조를 검증하기 위하여 JM 9.4부터 reference C를 개발하였으며, reference C로부터 test vector를 추출하며 설계 된 회로를 검증하였다. 제안된 회로는 최대 166MHz clock에서 동작하며, 합성결과 Charterd 0.18um 공정에 램 포함 약 180만 gate 크기이다. MPW제작시 chip size $6{\times}6mm$의 크기와 208 pin의 Pakage 형태로 제작하였다.

• 한국통신학회논문지
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• 제9권1호
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• pp.1-10
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• 1984

時分割多重化方式에 의한 Telemetry用 PCM encoder를 塔載型遠幅測定에 適合하도록 國産化開發硏究를 追究하였다. Program switch에 의하여 選擇되는 PCM encoder의 analog人力채널은 0~64word/frame($\pm$5V full scale), discrete人力은 0~30bit(5V$\pm$1V or 0V$\pm$1V dc)이며 bit rate는 70 및 140Kbit/sec, 分解能力은 8~12bit/word를 選擇할 수 있다. 그리고 filtered output code는 5次Bessel型LPF($f_{c}$=100kHz)를 통한 NRZ-L 및 Bi$\phi$=S이며 PCM encoder의 시스템誤差는 full scale에 대하여 最大 $\pm$0.2%이다.

• International Journal of Precision Engineering and Manufacturing
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• 제8권2호
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• pp.20-25
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• 2007

This paper describes a second-generation dual sine-grid surface encoder for 2-D position measurements. The surface encoder consisted of a 2-D grid with a 2-D sinusoidal pattern on its surface, and a 2-D angle sensor that detected the 2-D profile of the surface grid The 2-D angle sensor design of previously developed first-generation surface encoders was based on geometric optics. To improve the resolution of the surface encoder, we fabricated a 2-D sine-grid with a pitch of $10{\mu}m$. We also established a new optical model for the second-generation surface encoder that utilizes diffraction and interference to generate its measured values. The 2-D sine-grid was fabricated on a workpiece by an ultra precision lathe with the assistance of a fast tool servo. We then performed a UV-casting process to imprint the sine-grid on a transparent plastic film and constructed an experimental setup to realize the second-generation surface encoder. We conducted tests that demonstrated the feasibility of the proposed surface encoder model.

• 방송공학회논문지
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• 제17권6호
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• pp.1091-1105
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• 2012

본 논문에서는 현재 표준화가 진행 중인 HEVC (high efficiency video coding) 부호화기의 고속화, 최적화, 병렬화 연구에 앞서 통계적 특성 및 복잡도 분석을 수행하였다. HEVC는 H.264/AVC에 비해 약 2배의 압축 성능을 나타내지만 부호화기 복잡도는 크게 증가하여 이는 앞으로 해결해야할 문제로 남아있다. HEVC의 높은 부호화기 복잡도를 해결하기 위한 고속화, 최적화, 병렬화 연구에 앞서, 본 논문에서는 HEVC 참조소프트웨어인 HM 7.1을 이용하여 HEVC 부호화기의 복잡도를 측정하였다. 추가적으로, 실제 응용에서 사용될 고속 HEVC 부호화기 소프트웨어에 대한 예상 복잡도를 고속 알고리듬이 적용된 HM 7.1 소프트웨어로 측정하였다. 복잡도 측정은 공통 실험 영상 및 조건을 사용하였으며 PC 환경에서 부호화기 소프트웨어의 동작 사이클을 측정하고 이를 분석하였다. 또한, 부호화를 통해 생성된 비트스트림을 이용하여 HEVC 부호화기 소프트웨어의 부호화 구조에 따른 통계적 특성과 제한적 부호화에 따른 통계적 특성에 대하여 제시하고 이를 분석한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 B
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• pp.1003-1005
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• 2002

In general, to get the accurate switching point of power electronic components is dependent on a given rotor position by the encoder. However, a conventional encoder may not be used to detect position and speed of the developed motor due to the very high speed. Thus, an encoder that uses the hall effect directly was designed and applied. This paper presents the developed encoder that meet requirement of military purpose. To confirm the developed encoder, the experimental results are shown.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제8권1호
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• pp.75-81
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• 2008

This paper presents a top-down approach to implement an MPEG-2 audio encoder in VLSI. As the algorithm of an MPEG-2 audio encoder is heavy-weighted and heterogeneous(to be mixture of several strategies), the encoder design process is undertaken carefully from the algorithmic level to the architectural level. Firstly, the encoding algorithm is analyzed and divided into sub-algorithms, called tasks, and the tasks are partitioned in the way of reusing the same designs. Secondly, the partitioned tasks are scheduled and synthesized to make the most efficient use of time and space. In the end, a real-time 5 channel MPEG-2 audio encoder is designed which is a heterogeneous multiprocessor system; two hardwired logic blocks and one specialized DSP processor.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.260-264
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• 2005

This paper describes the ultra precise position control of servo motor using sinusoidal encoder based on 'Arcsine Interpolation Method'. First, the paper theoretically analyzes and verify throughout experiments, the relationship between A/D converter input ripple and the total resolution to measure the precise position. Second, this paper presents a way to compensate the total gain and offset error by utilizing a low cost programmable differential amp, by which without any special expensive equipments they are easily on-line tuned and effectively compensated. Lastly, it was compared to servomotor position control characteristics using digital incremental 50,000ppr encoder. The test results show that, with much cheaper sinusoidal encoder, the proposed method exhibits better performance both in position control and ASD applications than the 50,000ppr optical encoder.

• International Journal of Contents
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• 제9권1호
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• 한국생산제조학회지
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• 제9권3호
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• pp.103-110
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• 2000

Shaft encoder which encodes the rotational angle of a shaft becomes more important recently due to factory automation and office automation. Although an absolute type encoder is more dsirable due to its convenience an incremental encoder is commonly used because of its cost and technical difficulties Fabricating a high resolution absolute encoder is very diff-cult because the physical size is limited by currently available technology. In order to overcome this difficulty Moire fringe can be used incorporated with gray code. In order to measure the position of fringes which move as the code disk rotates a neural network was developed in this paper. Formerly fringe position is usually measured by a sophisticated software which needs a little long calculation time. However using nerual network method can eliminate such calculation time even though it needs learning job The pro-posed method is verified through several experiments.