• Title/Summary/Keyword: ELM-MAC

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Implementation and Performance Evaluation of ELM-MAC Protocol for Energy Efficiency in Sensor Networks (센서 네트워크에서 에너지 효율을 위한 ELM-MAC 프로토콜의 구현 및 성능평가)

  • Yun, Phil-Jung;Kim, Chang-Hwa;Kim, Sang-Kyung
    • Journal of the Korea Society for Simulation
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    • v.17 no.4
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    • pp.81-88
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    • 2008
  • It is important to study the energy efficient MAC protocol in sensor networks. We propose a new protocol named as ELM?MAC (Energy efficient Link Management MAC) to increase energy efficiency in sensor networks. ELM-MAC protocol operates, uses, and manages the optimized transmission power level to increase energy efficiency in MAC layer. It includes mechanism that uses the adaptive method in change of surround environment for guarantee of link quality. In this paper we implement ELM-MAC and evaluate its performance.

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An Implementation of Low Power MAC using Improvement of Multiply/Subtract Operation Method and PTL Circuit Design Methodology (승/감산 연산방법의 개선 및 PTL회로설계 기법을 이용한 저전력 MAC의 구현)

  • Sim, Gi-Hak;O, Ik-Gyun;Hong, Sang-Min;Yu, Beom-Seon;Lee, Gi-Yeong;Jo, Tae-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.4
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    • pp.60-70
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    • 2000
  • An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4:2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

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