• 조명전기설비학회논문지
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• 제22권4호
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• pp.93-99
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• 2008

휴대용 기기의 다양한 기능으로 인해 에너지 절약은 더욱 중요한 문제가 되고 있다. Dynamic Voltage Scaling(DVS)는 임베디드 기기에서 대표적으로 사용되는 에너지 절약 방법이다. 본 논문에서는 응용프로그램의 작업량 변화에 따라 프로세서의 동작 전압과 속도를 조절할 수 있는 DVS 알고리즘을 제안한다. 제안된 DVS 알고리즘은 커널의 DVS 모듈과 응용프로기램의 작업량 변화를 관찰하는 함수로 구성되어 있으며 작업량이 급격히 증가 하거나 감소하는 경우 이에 알맞은 프로세서의 동작 수준을 결정함으로서 작업의 데드라인을 넘기지 않으면서도 전력 소비를 줄일 수 있도록 하였다. 제안된 DVS 알고리즘은 Linux 2.6 커널과 PXA270프로세서를 이용한 임베디드 시스템에서 구현되었다.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2009년도 IWAIT
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권12호
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• pp.561-565
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• 2001

Recent trend of increasing automated factories needs supply of high quality power from the utilities. Among the items of the power quality, voltage sag can be compensated by Dynamic Voltage Restorer(DVR). The key feature of the DVR is high response with less transient period to recover from the voltage sag due to the lightning or line-to-ground faults. In this paper we report that $H_{\infty}$ controller is very promising for the practical application to the controller of DVR. Experimental results shown in this paper was obtained by applying the control algorithm to 20 kVA DVR system. The experimental set consists of IGBT-based three phase inverter and the TMS320C32-60 DSP used for main processor of the control board. To simulate the 50% voltage sag, the SCR-based experimental set was constructed.

• Journal of Computing Science and Engineering
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• 제4권3호
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• pp.189-206
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• 2010

It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-time applications in embedded system design. The effectiveness comes from the fact that the amount of energy consumption is quadractically proportional to the voltage applied to the processor. The penalty is the execution delay, which is linearly and inversely proportional to the voltage. According to the granularity of tasks to which voltage scaling is applied, the DVS problem is divided into two subproblems: inter-task DVS problem, in which the determination of the voltage is carried out on a task-by-task basis and the voltage assigned to the task is unchanged during the whole execution of the task, and intra-task DVS problem, in which the operating voltage of a task is dynamically adjusted according to the execution behavior to reflect the changes of the required number of cycles to finish the task before the deadline. Frequent voltage transitions may cause an adverse effect on energy minimization due to the increase of the overhead of transition time and energy. In addition, DVS needs to be carefully applied so that the dynamically varying chip temperature should not exceed a certain threshold because a drastic increase of chip temperature is highly likely to cause system function failure. This paper reviews representative works on the theoretical solutions to DVS problems regarding inter-task DVS, intra-task DVS, voltage transition, and thermal-aware DVS.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.38.2-38
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• 2001

Recent trend of increasing automated factories needs supply of high quality power from the utilities. Among the items of the power quality, voltage sag can be compensated by Dynamic Voltage Restorer(DVR). The key feature of the DVR is high response with less transient period to recover from the voltage sag due to the lightning or line-to-ground faults. In this paper we report that H controller is very premising for the practical application to the controller of DVR. Experiment al results shown in this paper was obtained by applying the control algorithm to 20 kVA DVR system. The experimental set consist s of IGBT - based three phase inverter and the TMS320C32- 60 DSP used for main processor of the control board. T$\infty$ simulate the 50% voltage ...

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅲ
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• pp.1379-1382
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• 2003

Recently, mobile embedded systems used widly in various applications. Managing power consumption is becoming a matter of primary concern because those systems use limited power supply. As an approach reduce power consumption, voltage can be scaled down. according to the execution time and deadline. By reducing the supplying voltage to 1/N power consumption can be reduced to 1/N. DPM-S is a well known method for dynamic voltage scaling. In this paper, we enhanced DPM-S by using average execution time aggressively. The frequency of processor is calculated based in average execution time instead of worst case execution time. Simulation results show that our method achieve up to 5％ energy savings than DPM-S.

• ETRI Journal
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• 제33권3호
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• pp.407-414
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• 2011

In an effort to reduce energy consumption, research into adaptive power management in real-time systems has become widespread. In this paper, a novel dynamic voltage scaling scheme is proposed for multiprocessor systems. Based on the concept of the Nash bargaining solution, a processor's clock speed and supply voltage are dynamically adjusted to satisfy these conflicting performance metrics. In addition, the proposed algorithm is implemented to react adaptively to the current system conditions by using an adaptive online approach. Simulation results clearly indicate that the superior performance of the proposed scheme can strike the appropriate performance balance between contradictory requirements.

• Journal of Power Electronics
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• 제13권3호
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• pp.400-408
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• 2013

This paper presents a discrete state-space controller using state feedback control and feed-forward decoupling to provide a desirable control bandwidth and control stability for dynamic voltage restorers (DVR). The paper initially discusses three typical applications of a DVR. The load-side capacitor DVR topology is preferred because of its better filtering capability. The proposed DVR controller offers almost full controllability because of the multi-feedback of state variables, including one-beat delay feedback. Feed-forward decoupling is usually employed to prevent disturbances of the load current and source voltage. Directly obtaining the feed-forward paths of the load current and source voltage in the discrete domain is a complicated process. Fortunately, the full feed-forward decoupling strategy can be easily applied to the discrete state-space controller by means of continuous transformation. Simulation and experimental results from a digital signal processor-based system are included to support theoretical analysis.

• ETRI Journal
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• 제42권4호
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• pp.468-479
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• 2020

The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function-safe architecture is proposed for a fault-tolerance system such as an electronics system for autonomous cars. The general-purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self-recovering cache and dynamic lockstep function. The function-safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28-nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function-safe design can have ISO26262 ASIL-D with the single-point fault-tolerance rate of 99.64%.