• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.743-754
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• 2006

In the proposed method, two regular laser working at two different wavelengths perform moving object detection alternatively in time. The laser intensity and the beaming period of each laser is equally maintain as to the single laser radar, hence, externally, dual beam lasers radar works exactly same as the single beam laser radar except that the proposed dual lasers radar needs additional post-processing of received signals in the receiver. To verify the robustness of the proposed method, a set of computer simulation has been performed. The communication channel is assumed to be additive white Gaussian noise, and the perfect synchronization is assumed. All other simulation parameters such as signal power and signalling period are equally maintain in both systems while the signal processing time such as spreading and filtering are expected to be trivial in call cases.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.9
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• pp.891-897
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• 2006

The coverage of the NDGPS is nationwide currently and by 2007 more than 2 NDGPS signal will be available in most of Korean peninsula both coastal area and inland. The role of NDGPS beacon is transmitting pseudorange corrections however if range or pseudorange can be measured from NDGPS beacon signal, it might be possible to construct an independent regional navigation system: The range from NDGPS beacon signal can be used as additional measurements to remove GPS shadow area and to improve accuracy and reliability of GPS. Furthermore, by adding Loran-C, a regional radio navigation system without GPS can be possible. In this paper, a feasibility study on the regional positioning system using NDGPS and LORAN-C are given. The results show that the NDGPS and LORAN-C can be used as a ground based regional navigation system if requirements such as synchronization of NDGPS network, dual coverage of NDGPS, navigation algorithm for both NDGPS and LORAN-C measurements and an efficient ASF compensation method are met.

• Journal of Drive and Control
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• v.13 no.2
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• pp.1-9
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• 2016

In this paper, an elementary force fighting problem was investigated. The problem is encountered when a double-rod type EHA(electro-hydrostatic actuator) is combined with a single-rod type EHA to build a redundant actuator system with synchronized motion. When the rod-side chambers of the two different types of EHAs have the same effective piston areas and are simultaneously pressurized by an external load, the two EHAs behave identically, sharing the external load equally. However, when the piston head-side chamber of the single rod type EHA, having a larger effective area than the rod-side chamber, is pressurized by the external load, an abnormal force fighting between the two EHAs occurs, unless their pump speeds are properly decoupled. In this study, the output drive forces of each EHA were obtained from the cylinder pressure signals and applied to the position control for each EHA to maintain the balance between their pump speeds. Adding minor force difference feedback loops to the position control, the force fighting phenomena could be eliminated and steady state synchronization errors were reduced. The power consumption of the pumps also could be remarkably reduced, avoiding unnecessarily high load pressures to the pumps.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.542-546
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• 2008

Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to maintain memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target applications: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we allow simultaneous accesses to different blocks thus achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result - we could achieve about 20-50% performance gain compared to the base DPSDRAM architecture.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.6
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• pp.703-709
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• 2014

In the AMP(Asymmetric Multiprocessing) based dual core using core-specific operating system in a single processor system, shared memory method is used to send data between processors in dual core. To used shared memory in different operating systems, there is a problem of needing to solving the issue of message communication and synchronization between the two operations systems. In this paper, separate memory controller was used for data sharing between different processor cores in dual core environment. This controller can designate two slave ports to allow simultaneous access from two processors, and in the case of process data simultaneously by two processors, priority order of slave ports is determined through memory mediator. When sending data from A to B processor, SRAM area was logically separated into 8 pages. It allowed using memory area from multiple processes with the size of 4KByte per page, and control register with the size of 4Byte was used to discern the usability of current page.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.816-821
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• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.3
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• pp.941-955
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• 2015

In dual-channel networks (DCNs), all frequency hopping (FH) sequences used for data channels are chosen from the original FH sequence used for the control channel by shifting different initial phases. As the number of data channels increases, the hitting frequency point problem becomes considerably serious because DCNs is non-orthogonal synchronization network and FH sequences are non-orthogonal. The increasing severity of the hitting frequency point problem consequently reduces the resource utilization efficiency. To solve this problem, we propose a novel hitting frequency point collision avoidance method, which consists of a sequence-selection strategy called sliding correlation (SC) and a collision avoidance strategy called keeping silent on hitting frequency point (KSHF). SC is used to find the optimal phase-shifted FH sequence with the minimum number of hitting frequency points for a new data channel. The hitting frequency points and their locations in this optimal sequence are also derived for KSHF according to SC strategy. In KSHF, the transceivers transmit or receive symbol information not on the hitting frequency point, but on the next frequency point during the next FH period. Analytical and simulation results demonstrate that unlike the traditional method, the proposed method can effectively reduce the number of hitting frequency points and improve the efficiency of the code resource utilization.

• Journal of Chest Surgery
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• v.46 no.4
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• pp.289-292
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• 2013

Through the use of a dual chamber (DDD) pacemaker, we achieved a cardiac resynchronization effect in a 51-year-old female patient who was transferred to our hospital from another hospital for an operation for three-vessel coronary artery disease. Her electrocardiogram showed a left bundle branch block (LBBB) and a prolonged QRS interval of 166 milliseconds. Severe left ventricle (LV) dysfunction was diagnosed via echocardiography. Coronary artery bypass grafting (CABG) was then performed. In order to accelerate left atrial activation and reduce the conduction defect, DDD pacing using right atrial and left and right ventricular pacing wires was initiated postoperatively. The cardiac output was measured immediately, and one and twelve hours after arrival in the intensive care unit. The cardiac output changed from 2.8, 2.4, and 3.6 L/min without pacing to 3.5, 3.4, and 3.5 L/min on initiation of pacing. The biventricular synchronization using DDD pacing was turned off 18 hours after surgery. She was transferred to a general ward with a cardiac output of 3.9 L/min. In patients with coronary artery disease, severe LV dysfunction, and LBBB, cardiac resynchronization therapy can be achieved through DDD pacing after CABG.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1836-1839
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• 2005

We have developed Ethernet based real-time communication systems called "Vnet/IP" for DCS which is the control system for process automation. This paper describes the features and the technologies of the ASIC which is utilized in the communication interface hardware for Vnet/IP. Vnet/IP has been developed for mission-critical communications. Hence it has real-time feature, high reliability and precise time synchronization capability. At the same time, it is able to deal with standard protocols without influence on mission-critical communications. The communication interface hardware has a host interface and dual redundant network interfaces. The host interface can be chosen PCI-bus or R-bus which is the proprietary internal bus developed for the high reliable redundant controller. Each network interface is a RJ45 connection with 1Gbps maximum in compliance with IEEE802.3.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.260-268
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• 1990

This paper investigates the design of a frequency hopping FSK tranceiver system, where the system enhancements are made in the following three aspects: dual frequency synthesiszation for the increased hopping rate, linearization of VCO gain in PLL to improve BFSK modulation characteristics, and fast code synchronization by the matched filter method.