• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.267-269
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• 2003

반도체 웨이퍼 및 각종 박막의 면/비저항(sheet/resistivity resistance)의 측정에 비교적 간단히 측정할 수 있고 측정정확도가 높은 4탐침(four-point probe)방법이 널리 사용되고 있다 또한 4탐침 측정방법은 높은 분해능의 contour map작성과 ion implantation의 doping accuracy 및 doping uniformity의 측정에도 사용된다. 최근 재료의 소형, 박막화 경향으로 볼 때 정확한 비저항 측정의 필요성이 요구되고 있으며 이에 따라 4탐침 측정기술인 single 및 dual configuration method로 실리콘 웨이퍼에 대한 비저항의 측정 정확도를 고찰한 결과 dual configuration 측정방법이 single configuration측정 방법에 비하여 정밀 정확도가 더 좋은 것으로 고찰되었다.

• Transactions on Electrical and Electronic Materials
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• v.11 no.3
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• pp.120-125
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• 2010

For the fabrication of PMOS and integrated semiconductor devices, B, $BF_2$ and dual elements with B and $BF_2$ can be implanted in silicon. 15 keV B ions were implanted in silicon at $7^{\circ}$ wafer tilt and a dose of $3.0{\times}10^{16}\;cm^{-2}$. 67 keV $BF_2$ ions were implanted in silicon at $7^{\circ}$ wafer tilt and a dose of $3.0{\times}10^{15}\;cm^{-2}$. For dual implantations, 67 keV $BF_2$ and 15keV B were carried out with two implantations with dose of $1.5{\times}10^{15}\;cm^{-2}$ instead of $3.0{\times}10^{15}\;cm^{-2}$, respectively. For the electrical activation, the implanted samples were annealed with rapid thermal annealing at $1,050^{\circ}C$ for 30 seconds. The implanted profiles were characterized by using secondary ion mass spectrometry in order to measure profiles. The implanted and annealed results show that concentration profiles for the ${BF_2}^+$ implant are shallower than those for a single $B^+$ and dual ($B^+$ and ${BF_2}^+$) implants in silicon. This effect was caused by the presence of fluorine which traps interstitial silicon and ${BF_2}^+$ implants have lower diffusion effect than a single and dual implantation cases. For the fabricated diodes, current-voltage (I-V) and capacitance-voltage (C-V) were also measured with HP curve tracer and C-V plotter. Electrical measurements showed that the dual implant had the best result in comparison with the other two cases for the turn on voltage characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.37-42
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• 2004

Shallow $p^{＋}$-n junctions were formed by preamorphization, low-energy ion implantation and dual-step annealing processes. Germanium ions were implanted into silicon substrates for preamorphization. The dopant implantation was performed into the preamorphized and non-preamorphized substrates using B $F_2$2 ions. Rapid thermal anneal (RTA) and furnace anneal (FA) were employed for dopant activation and damage removal. Samples were annealed by one of the following four methods; RTA(75$0^{\circ}C$/10s)＋Ft FA＋RTA(75$0^{\circ}C$/10s), RTA(100$0^{\circ}C$/10s)＋FA, FA＋The Ge Preamorphized sample exhibited a shallower junction depth than the non-preamorphized sample. When the employed RTA temperature was 100$0^{\circ}C$, FA＋RTA annealing sequence exhibited better junction characteristics than RTA＋FA thermal cycle from the viewpoint of junction depth, sheet resistance, $R_{s}$$.$ $x_{j}$, and leakage current.t.