• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.18 no.1
• /
• pp.15-29
• /
• 2024

A fetoscope is an optical endoscope, which is often applied in fetoscopic laser photocoagulation to treat twin-to-twin transfusion syndrome. In an operation, the clinician needs to observe the abnormal placental vessels through the endoscope, so as to guide the operation. However, low-quality imaging and narrow field of view of the fetoscope increase the difficulty of the operation. Introducing an accurate placental vessel segmentation of fetoscopic images can assist the fetoscopic laser photocoagulation and help identify the abnormal vessels. This study proposes a method to solve the above problems. A novel encoder-decoder network with a dual-path structure is proposed to segment the placental vessels in fetoscopic images. In particular, we introduce a channel attention mechanism and a continuous convolution structure to obtain multi-scale features with their weights. Moreover, a switching connection is inserted between the corresponding blocks of the two paths to strengthen their relationship. According to the results of a set of blood vessel segmentation experiments conducted on a public fetoscopic image dataset, our method has achieved higher scores than the current mainstream segmentation methods, raising the dice similarity coefficient, intersection over union, and pixel accuracy by 5.80%, 8.39% and 0.62%, respectively.

• The Journal of Korea Robotics Society
• /
• v.7 no.1
• /
• pp.9-19
• /
• 2012

This paper proposes a performance index for the multiple shape object handling of dual arm manipulator to determine whether a robot is good or not. When the dual-arm manipulator grasps a fixed object and is posed, the dual-arm manipulator should procure a space to freely control the manipulator. As a performance evaluation parameter, each joint torque from current sensor signal is utilized. From the current information, torque and energy for each joint are estimated. In this paper an performance index for an unstructured object is defined by an energy-cost function, and stability analysis for each motion is derived by the maximum force to the object. The maximum force to the object is computed by the inertia of object and acceleration information of end-effector. The acceleration data are derived by the double derivation of each encoder signal. Manipulability measure which implies how efficiently the dual-arm manipulator can move with the grasped object, can be represented by the intersection of the two manipulability ellipsoids for the left and right arms. Effectiveness of the proposed algorithm has been verified through the practical simulations and real experiments.

• Proceedings of the KIEE Conference
• /
• 2006.07d
• /
• pp.2023-2024
• /
• 2006

1962년 Gallager에 의해 처음 제안된 LDPC 부호는 복호를 수행하는 부호방식으로 패리티 행렬(H)의 대부분이 0으로 구성되어 복호시에 적은 연산량을 요구하며, shannon의 한계에 도달하는 복호 능력으로, 차세대 통신의 주된 부호 방식으로 고려되고 있다. 하지만, LDPC는 부호화에 있어서 여타 다른 부호방식에 비해 복잡한 특성을 가지고 있으므로, 이를 개선하기 위한 부호방식의 적용이 필요하다. 본 논문에서는 효율 적인 부호화를 위하여 Dual-diagonal H parity행렬을 구성 하고, 쉽게 부호 길이를 확장 할 수 있는 Quasi-Cyclic 방식을 적용한 복호기를 구현하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.1 s.343
• /
• pp.27-36
• /
• 2006

Conventional delay-insensitive (DI) data encodings usually require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, an encoder and a decoder circuits, where N-bit data transfer can be peformed with only N+l wires, are proposed. These circuits are based on a quasi delay-insensitive (QDI) model and designed by using current-mode multiple valued logic (CMMVL). The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25 um CMOS technology. In general, simulation results with wire lengths of 4 mm or larger show that the CMMVL scheme significantly reduces delay-power product ($D{\ast}P$) values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. In addition, simulation results using the buffer-inserted dual-rail and 1-of-4 encodings for high performance with the wire length of 10 mm and 32-bit data demonstrate that the proposed CMMVL scheme reduces the D*P values of the dual-rail encoding with data rate of 4 MHz or more and 1-of-4 encoding with data rate of 25 MHz or more by up to $57.7\%\;and\;17.9\%,$ respectively.

• ETRI Journal
• /
• v.46 no.1
• /
• pp.82-95
• /
• 2024

As automated essay scoring (AES) has progressed from handcrafted techniques to deep learning, holistic scoring capabilities have merged. However, specific trait assessment remains a challenge because of the limited depth of earlier methods in modeling dual assessments for holistic and multi-trait tasks. To overcome this challenge, we explore providing comprehensive feedback while modeling the interconnections between holistic and trait representations. We introduce the DualBERT-Trans-CNN model, which combines transformer-based representations with a novel dual-scale bidirectional encoder representations from transformers (BERT) encoding approach at the document-level. By explicitly leveraging multi-trait representations in a multi-task learning (MTL) framework, our DualBERT-Trans-CNN emphasizes the interrelation between holistic and trait-based score predictions, aiming for improved accuracy. For validation, we conducted extensive tests on the ASAP++ and TOEFL11 datasets. Against models of the same MTL setting, ours showed a 2.0% increase in its holistic score. Additionally, compared with single-task learning (STL) models, ours demonstrated a 3.6% enhancement in average multi-trait performance on the ASAP++ dataset.

• Proceedings of the KIEE Conference
• /
• 2011.07a
• /
• pp.943-944
• /
• 2011

The position of the rotor in a spherical motor is usually measured by encoders. When using a encoder, It is possible to measure the angle in a very high resolution. However it is limited to measure a single-DOF using one encoder. So it is required to use 3 encoders to measure a 3-DOF. In order to connect the encoder and the motor, an additional mechanic linkages. Because of these reasons, it is difficult to apply it in various systems. Where the friction and inertia is increased when operating the motor. It could cause a negative effect in dynamic characteristic. In this paper present dual-image sensing system capable of measuring 3-DOF motions in real time eliminating the mechanical linkages. In addition we offer methods of converting sensors outputs to rotation angle which is used in the controller.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.1207-1210
• /
• 1998

차세대 DVD system의 audio 규격인 Dolby AC-3를 구현하는 방법으로 DSP 프로세서인 TMSC80을 사용하여 실시간 처리 가능한 하드웨어 바탕의 firmware 소프트웨어를 개발하는 방법으로 구현하고자 한다. 본 논문에서는 먼저 TMS320C80을 바탕으로 한 하드웨어 구현에 관해 논의한다. 하드웨어의 구조는 TMS320C80과 시스템 메모리로의 DRAM, 오디오 입력부인 ADC, 입력 데이터를 효과적으로 사용하기 위한 FIFO menory, 오디오 출력용인 dac, 디버깅 및 통신포트로 USB, RS-232,LPT와 MPEG-2 encoding보드 등 다른 보드와 연계를 위한 local-bus를 위한 dual port ram으로 구성된다. 오디오 입력은 최대 24bit 48kHz sampling까지 받을 수 있다.

• Information and Communications Magazine
• /
• v.25 no.12
• /
• pp.10-18
• /
• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Annual Conference on Human and Language Technology
• /
• 2019.10a
• /
• pp.333-338
• /
• 2019

인코더-디코더(Encoder-decoder)는 현대 기계 번역(Machine translation)의 가장 기본이 되는 모델이다. 인코딩은 마치 인간의 뇌가 출발어(Source language) 문장을 읽고 이해를 하는 과정과 유사하고, 디코딩은 뇌가 이해한 의미를 상응하는 도착어(Target language) 문장으로 재구성하는 행위와 비슷하다. 그렇다면 벡터로 된 인코더 표현은 문장을 읽고 이해함으로써 변화된 뇌의 상태에 해당한다고 볼 수 있다. 사람이 어떤 문장을 잘 번역하기 위해서는 그 문장에 대한 이해가 뒷받침되어야 하는 것처럼, 기계 역시 원 문장이 가진 의미를 제대로 인코딩해야 향상된 성능의 번역이 가능할 것이다. 본 논문에서는 뇌과학에서 뇌 동기화(Brain-to-brain coupling)라 일컫는 현상을 모방해, 출발어와 도착어의 공통된 의미를 인코딩하여 기계 번역 성능 향상에 도움을 줄 수 있는 이중 번역 기법을 소개한다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.6B
• /
• pp.1183-1190
• /
• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.