• Title/Summary/Keyword: Dual converter

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Development of Fuzzy Logic-Based Diagnosis Algorithm for Fault Detection Of Dual-Type Temperature Sensor for Gas Turbine System (가스터빈용 듀얼타입 온도센서의 고장검출을 위한 퍼지로직 기반의 진단 알고리즘 개발)

  • Young-Bok Han;Sung-Ho Kim;Byon-Gon Kim
    • The Journal of the Korea institute of electronic communication sciences
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    • v.18 no.1
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    • pp.53-62
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    • 2023
  • Due to the recent increase in new and renewable energy, gas turbine generators start and stop every day to supply high-quality power, and accordingly, the life span of high-temperature parts is shortened and the failure of combustion chamber temperature sensors increases. Therefore, in this study, we proposed a fuzzy logic-based failure diagnosis algorithm that can accurately diagnose and systematically detect the failure of the sensor when the dual temperature sensor used for gas turbine control fails, and to confirm the usefulness of the proposed algorithm We tried to confirm the usefulness of the proposed algorithm by performing various simulations under the matlab/simulink environment.

Control and Analysis of an Integrated Bidirectional DC/AC and DC/DC Converters for Plug-In Hybrid Electric Vehicle Applications

  • Hegazy, Omar;Van Mierlo, Joeri;Lataire, Philippe
    • Journal of Power Electronics
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    • v.11 no.4
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    • pp.408-417
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    • 2011
  • The plug-in hybrid electric vehicles (PHEVs) are specialized hybrid electric vehicles that have the potential to obtain enough energy for average daily commuting from batteries. The PHEV battery would be recharged from the power grid at home or at work and would thus allow for a reduction in the overall fuel consumption. This paper proposes an integrated power electronics interface for PHEVs, which consists of a novel Eight-Switch Inverter (ESI) and an interleaved DC/DC converter, in order to reduce the cost, the mass and the size of the power electronics unit (PEU) with high performance at any operating mode. In the proposed configuration, a novel Eight-Switch Inverter (ESI) is able to function as a bidirectional single-phase AC/DC battery charger/ vehicle to grid (V2G) and to transfer electrical energy between the DC-link (connected to the battery) and the electric traction system as DC/AC inverter. In addition, a bidirectional-interleaved DC/DC converter with dual-loop controller is proposed for interfacing the ESI to a low-voltage battery pack in order to minimize the ripple of the battery current and to improve the efficiency of the DC system with lower inductor size. To validate the performance of the proposed configuration, the indirect field-oriented control (IFOC) based on particle swarm optimization (PSO) is proposed to optimize the efficiency of the AC drive system in PHEVs. The maximum efficiency of the motor is obtained by the evaluation of optimal rotor flux at any operating point, where the PSO is applied to evaluate the optimal flux. Moreover, an improved AC/DC controller based Proportional-Resonant Control (PRC) is proposed in order to reduce the THD of the input current in charger/V2G modes. The proposed configuration is analyzed and its performance is validated using simulated results obtained in MATLAB/ SIMULINK. Furthermore, it is experimentally validated with results obtained from the prototypes that have been developed and built in the laboratory based on TMS320F2808 DSP.

Design of 2-Ch DC-DC Converter with Wide-Input Voltage Range of 2.9V~5.6 V for Wearable AMOLED Display (2.9V~5.6V의 넓은 입력 전압 범위를 가지는 웨어러블 AMOLED용 2-채널 DC-DC 변환기 설계)

  • Lee, Hui-Jin;Kim, Hak-Yun;Choi, Ho-Yong
    • Journal of IKEEE
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    • v.24 no.3
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    • pp.859-866
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    • 2020
  • This paper proposes a 2-ch DC-DC converter with a wide-input voltage range from 2.9V~5.6V for wearable AMOLED displays. For positive voltage VPOS, a boost converter is designed using an over-charged voltage permissible circuit (OPC) which generates a normal output voltage even if over-input voltage is applied, and a SPWM-PWM dual mode with 3-segmented power transistors to improve efficiency at light load. For negative voltage VNEG, a 0.5x regulated inverting charge pump is designed to increase power efficiency. The proposed DC-DC converter was designed using a 0.18-㎛ BCDMOS process. Simulation results show that the proposed DC-DC converter generates VPOS voltages of 4.6 V and VNEG voltage of -0.6V~-2.3V for input voltage of 2.9V to 5.6V. In addition, it has power efficiency of 49%~92%, output ripple voltage has less than 20 mV for load current range of 1 mA~70 mA.

Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique

  • Yang, Yil-Suk;Roh, Tae-Moon;Yeo, Soon-Il;Kwon, Woo-H.;Kim, Jong-Dae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.1
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    • pp.1-7
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    • 2009
  • This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

Modeling and Analysis of Variable Wind Speed Turbine System Using Back to Back Converter (Back to bock 컨버터를 갖는 가변속 풍력터빈 시스템의 모델링과 해석)

  • Kim, Eel-Hwan;Kang, Keong-Bo;Kim, Jae-Hong;Moon, Sang-Ho;Oh, Sung-Bo;Kim, Se-Ho
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.19 no.8
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    • pp.150-157
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    • 2005
  • This paper presents the simulation modeling and analysis of variable wind speed turbine system(VWTS) using the doubly fed induction generator(DFIG) connected the back to back converter system in the rotor side. In the simulation, using the model system which has the 660[kW] rated power, blade control and the dual converter system are modeled for verifying the control characteristics. The VWTS is controlled by the optimal pitch angle for maximum output power under the rated wind speed, and for the rated output power over the rated wind speed. And also power factor is controlled by the reactive power. To verify the effectiveness of the proposed method, simulation results are compared with the actual data from the V47 VWTS located in Hangwon wind farm in Jeju-Do. According to the comparison of these results, this method shows excellent performance.

Design of Fractional-N Digital PLL for IoT Application (IoT 어플리케이션을 위한 분수분주형 디지털 위상고정루프 설계)

  • Kim, Shinwoong
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.800-804
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    • 2019
  • This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

High Efficiency Rectenna for Wireless Power Transmission Using Harmonic Suppressed Dual-mode Band-pass Filter (고조파 억압 이중모드 대역통과 여파기를 이용한 2.45 GHz 고효율 렉테나 설계)

  • Hong, Tae-Ui;Jeon, Bong-Wook;Lee, Hyun-Wook;Yun, Tae-Soon;Kang, Yong-Cheol;Lee, Jong-Chul
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.8 no.6
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    • pp.64-72
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    • 2009
  • In this paper, a high efficiency 2.45 GHz rectenna with a microstrip patch antenna and a dual-mode band-pass filter in which the 2nd and 3rd harmonics are suppressed, is presented. From the experimental results, the 2.45GHz rectenna using 3rd harmonic suppressed dual-mode BPF shows the conversion efficiency of 41.6% with incident power density of 0.3 mW/cm2 and the received power of 1.66 mW. This result shows high conversion efficiency because the received power of this rectenna is lower than other rectennas to be compared with. This rectenna can be applied to the WPT (Wireless Power Transmission) field for energy harvesting. Also, it is expected to be used to provide the stand-by power for the low power devices for USN, and wireless power transfer in sensor application of MEMS devices.

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The Effect of Mixing Rate and Multi Stage Injection on the Internal Flow Field and Combustion Characteristics of DISI Engine Using Methanol-gasoline Blended Fuel at High Speed / High Load Condition (고속 고부하 상태의 DISI 엔진에서 메탄올-가솔린 혼합연료의 연료 혼합비와 2단 분사가 엔진 내부유동 및 연소특성에 미치는 영향)

  • Bae, Jinwoo;Seo, Juhyeong;Lee, Jae Seong;Kim, Ho Young
    • Transactions of the Korean Society of Automotive Engineers
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    • v.21 no.5
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    • pp.15-24
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    • 2013
  • Numerical studies were conducted to investigate the internal flow field and combustion characteristics of DISI engine with methanol blended in gasoline. Dual injection was applied and the characteristics were compared to single injection strategy. The amount of the fuel injection was corresponded to air-fuel ratio of each fuel for complete combustion. The preforming model in this study, software STAR-CD was employed for both modeling and solving. The operating speed condition were at 4000 rpm/WOT (Wide open throttle) where the engine was fully warmed. The results of single injection with M28 showed that the uniformity, equivalence ratio, in-cylinder pressure and temperature increased comparing to gasoline (M0). When dual injection was applied, there was no significant change in uniformity and equivalence ratio but the in-cylinder pressure and temperature increased. When M28 fuel and single injection was applied, the CO (Carbon monoxide) and NO (Nitrogen oxides) emission inside the combustion chamber increased approximately 36%, 9% comparing with benchmarking case in cylinder prior to TWC (Three Way Catalytic converter). When dual stage injection was applied, both CO and NO emission amount increased.

Design of Wide-Band, High Gain Microstrip Antenna Using Parallel Dual Slot and Taper Type Feedline (평행한 이중 슬롯과 Taper형 급전선로를 이용한 광대역, 고이득 마이크로스트립 안테나의 설계)

  • Lee, Sang-Woo;Lee, Jae-Sung;Kim, Chol-Soo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.3 s.118
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    • pp.257-264
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    • 2007
  • In this paper, we have designed and fabricated a wide-band and high gain antenna which can integrate a standard of IEEE 802.1la$(5.15\sim5.25\;GHz,\;5.25\sim5.35\;GHz,\;5.725\sim5.825\;GHz)$. We inserted a parallel dual slot into a rectangular patch to have wide-band, and we offset an element of capacitance from the slot by using coaxial probe feeding method. We also designed a converter of $\lambda_g/4$ impedance with taper type line so that wide-band impedance can be matched easily. We finally designed structure with $2\times2$ array in order to improve the antenna gain, and the final fabricated antenna could have a good return loss(Return loss$\leq$-10 dB) and a high gain(over 13 dBi) at the range of $5.01\sim5.95\;GHz(B/W\doteqdot940\;MHz)$.

An Antenna & RF System for Fly-away Satcom Terminal Application on Ka-band (Ka대역 위성통신용 fly-away 터미널 안테나 & RF 시스템 설계)

  • Park, Byungjun;Kim, Chunwon;Yoon, Wonsang;Lee, SeongJae
    • Journal of the Korea Institute of Military Science and Technology
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    • v.17 no.4
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    • pp.485-491
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    • 2014
  • An Antenna & RF system for a fly-away satcom terminal application on ka-band is presented in this paper. The Fly-away satellite terminal can be moved and operated by two person and adapt automatic satellite tracking system in order to decrease the tracking time. Additionally, for low-power consumption, compact size and light-weight, a dual reflector antenna is constructed using dual-offset gregorian antenna structure. For minimize weight, the reflector of the antenna is made of Magnesium. For low-power consumption and light-weight, the pHEMT MMIC compound devices is utilized. The Electronic Band-Gap(EBG) Low-Pass Filter(LPF) is designed for harmonic rejection. In the receiving part, Low-Noise Block converter(LNB) structure is designed for compact and lightweight. In this paper, fly-away satcom terminal with low-power consumption, compact size and light-weight is described with antenna system and RF system performances. Through the experimentation, fly-away terminal's EIRP is more than 50dBW, G/T is more than $17dB/^{\circ}K$.