• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.47 no.2
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• pp.153-160
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• 2019

Electro-mechanical actuator system for aircraft has advantages in compactness and its lightweight, compared to the hydraulic actuator system. Hinge line actuator has low air resistance and is suitable for special purpose such as stealth. This paper describes design contents of 10,000 lbf-in class dual redundant hinge line electro-mechanical actuator system for performance test. The control structure was designed to minimize impact of torque fighting. A mathematical model is proposed to analyze and validate the performances of actuator by comparison with experiment results.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.6
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• pp.689-694
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• 2014

An SPLC (Safety Programmable Logic Controller) must be designed to meet the highest safety standards, IEEE 1E, and should guarantee a level of fault-tolerance and high-reliability that ensures complete error-free operation. In order to satisfy these criteria, I/O modules, communication modules, processor modules and bus modules of the SPLC have been configured in triple or dual modular redundancy. The redundant modules receive the same data to determine the final data by the voting logic. Currently, the processor of each rx module performs the voting by deciding on the final data. It is the intent of this paper to prove the improvement on the current system, and develop a voting system for multiple data on a system bus level. The new system bus protocol is implemented based on a TCN-MVB that is a deterministic network consisting of a master-slave structure. The test result shows that the suggested system is better than the present system in view of its high utilization and improved performance of data exchange and voting.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.39-45
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• 2004

A design method is proposed for the sequence detection with fixed decision delay with less hardware complexity using the concept of the Voronoi diagram and its dual, the Delaunay tessellation. This detector design is based on the Fixed Delay Tree Search (FDTS) detection. The FDTS is a computationally efficient sequence detection algerian and has been shown to achieve near-optimal performance in the severe Intersymbol Interference (ISI) channels when combined with decision feedback equalization and the appropriate channel coding. In this approach, utilizing the information contained in the Voronoi diagram or equivalently the Delaunay tessellation, the relative location of the detector input sequence in the multi-dimensional Euclidean space is found without any computational redundancy, which leads to a reduced complexity implementation of the detector.

• Journal of Power Electronics
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• v.10 no.2
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• pp.155-164
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• 2010

This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.

• ETRI Journal
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• v.43 no.2
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• pp.313-323
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• 2021

The Joint Video Exploration Team (JVET) has studied future video coding (FVC) technologies with a potential compression capacity that significantly exceeds that of the high-efficiency video coding (HEVC) standard. The joint exploration test model (JEM), a common platform for the exploration of FVC technologies in the JVET, employs quadtree plus binary tree block partitioning, which enhances the flexibility of coding unit partitioning. Despite significant improvement in coding efficiency for chrominance achieved by separating luminance and chrominance tree structures in I slices, this approach has intrinsic drawbacks that result in the redundancy of block partitioning data. In this paper, an adaptive tree structure correlating luminance and chrominance of single and dual trees is presented. Our proposed method resulted in an average reduction of -0.24% in the Y Bjontegaard Delta rate relative to the intracoding of JEM 6.0 common test conditions.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.3
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• pp.81-86
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• 2006

This paper deals with a driving current fault monitor design methodology for a DDV actuation system which has a dual hydraulic power supply system, and triplex electric control capability. A fault existing among these redundant channels should be detected accurately and removed timely, and the remaining channels are to be reconfigured in order to compensate the role of a removed faulty channel. An integrated analysis on the aerodynamics, flight control laws, and DDV actuation system is essential for the design of an actuation system fault monitor. A method to define a fault transient boundary which specifies a maximum travel of an actuation system caused by the first faulty operation is proposed based on the top level requirement on the fault effect specified in MIL-F-8785C.