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Fixed Decision Delay Detector for Intersymbol Interference Channel  

Taehyun, Jeon (ETRI)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.41, no.9, 2004 , pp. 39-45 More about this Journal
Abstract
A design method is proposed for the sequence detection with fixed decision delay with less hardware complexity using the concept of the Voronoi diagram and its dual, the Delaunay tessellation. This detector design is based on the Fixed Delay Tree Search (FDTS) detection. The FDTS is a computationally efficient sequence detection algerian and has been shown to achieve near-optimal performance in the severe Intersymbol Interference (ISI) channels when combined with decision feedback equalization and the appropriate channel coding. In this approach, utilizing the information contained in the Voronoi diagram or equivalently the Delaunay tessellation, the relative location of the detector input sequence in the multi-dimensional Euclidean space is found without any computational redundancy, which leads to a reduced complexity implementation of the detector.
Keywords
Intersymbol interference; Euclidean distance; Voronoi diagram; decision feedback equalization;
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