• Title/Summary/Keyword: Dual Port Memory

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ATM망의 비연결형 서버를 위한 고속 CAM ASIC 설계 (ASIC design of high speed CAM for connectionless server of ATM network)

  • 백덕수;김형균;이완범
    • 한국통신학회논문지
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    • 제22권7호
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    • pp.1403-1410
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    • 1997
  • Because streaming mode connection server suitable to wide area ATM networks performs transmission, reception and lookup with time restriction for the transmission time of a cell, it has demerits of large cell loss incase that burst traffic occurs. Therefore, in this paper to decrease cell loss we propose a high speed CAM (Content Addressable Memory) which is capable of processing data of streaming mode connections server at a high speed. the proposed CAM is applied to forwarding table VPC map which performs function to output connection numbers about input VPI(Virtual Path Identifier)/VCI(Virtual Channel Identifier). The designed high speed CAM consist of DBL(Dual Bit Line) CAM structure performed independently write operation and match operation and two-port SRAM structure. Also, its simulation verification and full-custom layout is performed by Hspice and Composs tools in 0.8 .$\mu$m design rule.

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고속병렬컴퓨터(SPAX)에서의 효율적인 메시지 전달을 위한 메시지 전송 기법 (A Message Transfer Scheme for Efficient Message Passing in the Highly Parallel Computer SPAX)

  • 모상만;신상석;윤석한;임기욱
    • 전자공학회논문지B
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    • 제32B권9호
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    • pp.1162-1170
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    • 1995
  • In this paper, we present a message transfer scheme for efficient message passing in the hierarchically structured multiprocessor computer SPAX(Scalable Parallel Architecture computer based on X-bar network). The message transfer scheme provides interface not only with operating system but also with end users. In order to transfer two types of control message and data message efficiently, it supports both of memory-mapped transfer and DMA-based transfer. Dual-port RAMs are used as message buffers, and control and status registers provide efficient programming interface. Interlaced parity scheme is adopted for error control. If any error is detected at receiving node, errored packet is resent by sender according to retry mechanism. In conjunction with retry mechanism, watchdog timers are used to protect infinite waiting and repeated retry. The proposed message transfer scheme can be applied to input/output nodes and communication connection nodes as well as processing nodes in the SPAX.

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Car Parking Lot 모니터링 시스템 (Monitoring System with PLC I/O for Car Parking Lot)

  • 이성재;김재양
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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    • pp.511-512
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    • 2007
  • The monitoring system has won acceptance as a premium mark that identifies the highest standard of product quality in advanced industry. The TOP features with multi-I/O ports and VGA & RCA TV-out ports supporting mirroring & multiple dual-display modes by windows 0/5. With the choice of versatile stands, panel mount, or VESA wall-mount swing arm and connecting to modem. Wireless keyboard, Customer Display and Card Reader, is your idea Panel system for the application of TOP(Touch Operation Pannel), KIOSK, or Office / Factory Automation. TOP is the hardware and software product that transacts all kind of functions for advanced technology equipment to button, switch, voice and graph etc so that let consumer use easily Industrial HMI System Touch Panel. System characteristics: Easy of use and flexibility to the user, Present a high value solution and advanced function for many Application, Factory Automation, Office Automation, Building Automation System, Information Service System, etc. Analog Touch - 2MB Flash Memory for Saving Screen Data - RS-232C/422 Serial Port - Multi Language Support.

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라인메모리 유형에 따른 이미지 처리 속도의 분석 (Analysis of the Image Processing Speed by Line-Memory Type)

  • 한시연;정세민;강봉순
    • 전기전자학회논문지
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    • 제27권4호
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    • pp.494-500
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    • 2023
  • 영상처리는 현재 다양한 분야에서 활용되고 있다. 그중 자율주행 자동차, 의료 영상처리, 로봇 제어 등은 빠른 영상처리 응답 속도가 필요하다. 이를 충족하기 위해 실시간 처리를 위한 하드웨어 설계가 활발히 연구되고 있다. 하드웨어 처리 속도는 입력 영상의 크기 외에도, 이미지에서 라인과 프레임을 구분하는 비활성화 영상 공백 구간의 크기에 영향을 받는다. 본 논문에서는 비활성화 영상 공백 구간과 밀접한 관련이 있는 라인메모리 유형에 따라 세 가지 스케일러 구조를 설계한다. 이 구조들은 Verilog 표준 언어를 사용하여 하드웨어로 설계되고, Xilinx Vivado 2023.1을 이용하여 field programmable gate array 환경에서 논리회로로 합성된다. 합성된 결과는 실시간 처리할 수 있는 표준 이미지 크기를 비교하면서 프레임 레이트 분석에 사용된다.