• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.3 s.357
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• pp.1-6
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• 2007

A drain bias switching technique is presented to enhance power added efficiency for WiBro and wireless LAN dual band and dual mode transmitter. Some simulations have been done to predict the effect of drain and gate bias change, and bias switching is proposed to get the higher efficiency for dual mode transmitter which generates different output power for different applications. With drain bias switching and simulated optimum fixed gate bias, the amplifier shows dramatic PAE improvement compared to the amplifier without bias switching. The drain and gate bias switching technique will be useful for multi mode communication system with various functions.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.107-111
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• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• Journal of Advanced Marine Engineering and Technology
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• v.32 no.8
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.52-56
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• 2014

In this paper, a high-efficiency power amplifier is implemented using a gate and drain bias control circuit for WPT (Wireless Power Transmission). This control circuit has been employed to improve the PAE (Power Added Efficiency). The gate and drain bias control circuits consists of a directional coupler, power detector, and operation amplifier. A high gain two-stage amplifier using a drive amplifier is used for the low input stage of the power amplifier. The proposed power amplifier that uses a gate and drain bias control circuit can have high efficiency at a low and high power level. The PAE has been improved up to 80.5%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.239-244
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• 2017

We experimentally investigate the physical mechanism for asymmetrical degradation in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses. The transfer curves exhibit an asymmetrical negative shift after the application of gate-to-source ($V_{GS}$) and drain-to-source ($V_{DS}$) bias stresses of ($V_{GS}=24V$, $V_{DS}=15.9V$) and ($V_{GS}=22V$, $V_{DS}=20V$), but the asymmetrical degradation is more significant after the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20 V) nevertheless the vertical electric field at the source is higher under the bias stress ($V_{GS}$, $V_{DS}$) of (24 V, 15.9 V) than (22 V, 20 V). By using the modified external load resistance method, we extract the source contact resistance ($R_S$) and the voltage drop at $R_S$ ($V_{S,\;drop}$) in the fabricated a-IGZO TFT under both bias stresses. A significantly higher RS and $V_{S,\;drop}$ are extracted under the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20V) than (24 V, 15.9 V), which implies that the high horizontal electric field across the source contact due to the large voltage drop at the reverse biased Schottky junction is the dominant physical mechanism causing the asymmetrical degradation of a-IGZO TFTs under simultaneous gate and drain bias stresses.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.89-90
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• 2007

In this paper, we propose Doherty amplifier with proper drain bias line. By $\lambda$/4 microstrip line, IMD is eliminated. Also output power of amplifier is reduced in wanted bandwidth. For linearity improvement, we design drain bias with narrow $\lambda$/4 microstrip line. We observe that gain characteristics improve 1dB and $3^{rd}/5^{th}$ IMD characteristics reduce 5dB/10dB.

• Journal of Sensor Science and Technology
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• v.28 no.5
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• pp.329-333
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• 2019

Solution-processed oxide thin-film transistors (TFTs) have garnered great attention, owing to their many advantages, such as low-cost, large area available for fabrication, mechanical flexibility, and optical transparency. Negative bias stress (NBS)-induced instability of sol-gel IGZO TFTs is one of the biggest concerns arising in practical applications. Thus, understanding the bias stress effect on the electrical properties of sol-gel IGZO TFTs and proposing an effective recovery method for negative bias stressed TFTs is required. In this study, we investigated the variation of transfer characteristics and the corresponding electrical parameters of sol-gel IGZO TFTs caused by NBS and positive bias recovery (PBR). Furthermore, we proposed an effective PBR method for the recovery of negative bias stressed sol-gel IGZO TFTs. The threshold voltage and field-effect mobility were affected by NBS and PBR, while current on/off ratio and sub-threshold swing were not significantly affected. The transfer characteristic of negative bias stressed IGZO TFTs increased in the positive direction after applying PBR with a negative drain voltage, compared to PBR with a positive drain voltage or a drain voltage of 0 V. These results are expected to contribute to the reduction of recovery time of negative bias stressed sol-gel IGZO TFTs.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.1
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• pp.77-83
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• 2011

In this thesis, 50W Doherty amplifier was designed and implemented for Beyond 3G's repeater and base-station. Auxiliary amplifier of doherty amplifier was implemented by Gate bias control circuit. Though gate bias control circuit solved auxiliary's bias problem, output characteristics of doherty amplifier was limited. To enhance the output characteristic relativize Drain control circuit And To improve power efficiency make 3-way Doherty power amplifier. therefore, 3-way GDCD (Gate and Drain bias Control Doherty) power amplifier is embodied to drain bias circuit for General Doherty power amplifier. The 3-way GDCD power amplifier composed of matching circuit with chip capacitor and micro strip line using FR4 dielectric substance of specific inductive capacity(${\varepsilon}r$) 4.6, dielectric substance height(H) 30 Mills, and 2.68 Mills(2 oz) of copper plate thickness(T). Experiment result satisfied specification of amplifier with gains are 57.03 dB in 2.11 ~ 2.17 GHz, 3GPP frequency band, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and ACLR characteristics at 5MHz offset frequency band station is -40.45 dBc. Especially, 3-way DCHD power amplifier showed excellence efficiency performance improvement in same ACLR than general doherty power amplifier.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.3
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• pp.40-47
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• 2009

This paper presents new drain bias scheme for the linearity enhancement of envelope tacking power amplifiers for W-CDMA base-stations. In the conventional envelope tracking power amplifiers, the drain bias voltage is lowered close to the knee voltage of transistor, resulting in the severe linearity degradation. To solve this problem, it is proposed in this paper that the amplifier is biased in the conventional class AB mode with a fixed drain bias voltage if the input envelope is low and in the envelope tracking mode otherwise. Moreover, the drain bias in the envelope tracking mode is newly determined to minimized the distortion. To verify the effectiveness of the proposed bias scheme, simulation is performed on the W-CDMA based-station envelope tracking power amplifier using class AB Si-LDMOS power amplifier. It is shown from the simulation that the proposed bias scheme allows a drastic linearity enhancement with the comparable efficiency enough to meet the requirement of W-CDMA base-station without additional linearization techniques.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.41-45
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• 2014

In this paper, a high-efficiency power amplifier is implemented by using a drain bias control circuit operated at low input power for WPT(Wireless Power Transfer). Adaptive bias control circuit was added to high-efficiency class-E amplifier. It was possible to obtain the overall improvement in efficiency by adjusting the drain bias at low input power. The proposed adaptive class-E amplifier is implemented by using the input and output matching network and serial resonant circuit for improvement in efficiency. Drain bias control circuit consists of a directional coupler, power detector, and operational amplifier for adjusting the drain bias according to the input power. The measured results show that output powers of 41.83 dBm were obtained at 13.56 MHz. At this frequency, we have obtained the power added efficiency(PAE) of 85.67 %. It was confirmed increase of PAE of an average of 8 % than the fixed bias from the low input power level of 0 dBm ~ 6 dBm.