• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.177-180
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• 2000

This paper proposes the optimized hardware architecture for a high performance image downscaler The proposed downscaler uses non-linear digital filters for horizontal and vertical scalings. In order to achieve the optimization, the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The performance of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using the VHDL and implemented by using the IDEC-C632 0.65$\mu\textrm{m}$ cell library.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.265-268
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• 2000

In this paper, we propose an algorithm, an optimized architecture, and an implementation for an improved performance of image downscaler. The proposed downscaler uses two-dimensional digital filters for horizontal and vertical scalings, respectively. It also improves scaling precisions and decreases the loss of data, compared with the 1/32 scaler 〔1〕. In order to achieve the optimization, the digital filters are implemented by the multiplexer -adder type scheme 〔2〕. The scaler is designed by using the Verilog-HDL. It is synthesized into gates by using the Samsung 0.35 um STD90 TLM library.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.344-347
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• 1999

본 논문에서는 이차원 위상-교정 디지털필터를 이용한 고화질 디지털 영상축소기에 관한 알고리듬과 하드웨어 구조를 제안한다. 제안된 축소기는 수직방향으로 1/32 line과 수평방향으로 1/64 pixel의 정밀도를 가진 비선형 위상 필터를 사용하여 고화질의 축소 화상을 제공한다. 최적화된 하드웨어 구조를 달성하기 위하여, 디지털필터는 shifter와 adder를 이용하여 구성한다. 마지막으로 시뮬레이션을 통해서 기존의 1/32scale[1]의 결과와 비교하여 제안된 방법의 우수성을 보인다.