• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2176-2182
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• 2014

In this paper, a phase locked loop with suppressed power supply noise has been proposed. The added negative feedback loop of voltage controlled oscillator(VCO) and power noise detector suppresses the power noise induced jitter variation of VCO down to 1/3. The power noise detector is the modified circuit of frequency voltage converter. The proposed PLL has been designed based on a 1.8V 0.18um CMOS process and proved by HSPICE simulation.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1958-1960
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• 2003

Here we describe a unique self-oscillating mixer (SOM) design using a modified defected ground structure (DGS) for down-converter. Proposed SOM is consisted of self-oscillator, which can produce negative resistance and select resonance frequency, and input/output matching filter. As the advantage of this SOM can be reused by module that mix signals with transistor that is used to oscillator, it is simply and low-costly designed Also, there is easy advantage to be applied in RFIC/ MMIC technology because it offers excellent high Q value in spite of using micro-strip structure. Designed self-oscillating frequency is 1.04GHz and RF frequency established is 0.8GHz. It was achieved 20dB conversion loss and phase noise of -95dBc/Hz at 100KHz offset frequency over intermediate frequency (IF). The equivalent circuit parameters for DGS are extracted by using a three dimensional EM simulator and simple circuit analysis method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.2
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• pp.75-81
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• 2015

At the end of the 19th century, Edison's DC power system and Tesla's AC power system was debated in power market. Finally, AC system became the primary system of the power market because both step-up and step-down of voltage by using transformer and long-distance power transmission are easily possible. However, nowadays the power market takes some action for introducing DC system. Both domestic and foreign researchers are conducting the study on the DC system as well. Some researchers have conducted the studies on power quality and economic evaluation of the DC distribution system but DC distribution system is still controversial in terms of the effectiveness and reliability. In this paper, we calculate the reliability indices of the Low Voltage Direct Current(LVDC) distribution system considering arrangement of power electronics, layout of the distribution system, and distance between load points.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.227-231
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• 2004

A MMIC (Monolithic Microwave Integrated Circuit) mixer chip using the schottky diode of InGaAs/CaAs p-HEMT process has been developed for receiver down converter of Ka-band. A different approach of MMIC mixer structure is applied for reducing the chip size by the exchange of ports between IF and LO. This MMIC covers with RF (30.6∼31.0㎓)and IF (20.8∼21.2㎓). According to the on-wafer measurement, the MMIC mixer with miniature size of 3.0mm1.5mm demonstrates conversion loss below 7.8㏈, LO-to-RF isolation above 27㏈, LO-to-IF isolation above 19㏈ and RF-to-IF isolation above 39㏈, respectively.

• Journal of the Korea Institute of Military Science and Technology
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• v.22 no.3
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• pp.332-340
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• 2019

Electronic warfare systems are needed to be advantageous in the modern war. Many radar threat signals with various frequency spectrums and complicated techniques exist. For detecting the threats, a receiver with wide and narrow-band digital processing is needed. To process a wide-band searching mode, a polyphase filter bank has become the architecture of choice to efficiently detect threats. A polyphase N-path filter aligns the re-sampled time series in each path, and a discrete Fourier transform aligns phase and separates the sub-channel baseband aliases. Multiple threats and CW are detected or rejected when the signals are received in different sub-channels. And also, to process a narrow-band precision mode, a direct down converter is needed to reduce aliasing by using a decimation filter. These digital logics are designed in a FPGA. This paper shows how to design and develop a wide and narrow-band digital receiver that is capable to detect the threats.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.147-152
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• 2022

This study describes the design and implementation of EGSE for Dehop/Rehop Transponder. The EGSE is a equipment that evaluates Dehop/Rehop Transponder and requires precise and accurate measurement. EGSE consists of a PLDIU and IIU(Instrument Interface Unit), Up/Down converter for L band, Modems to verify the Dehop/Rehop Transponder. The EGSE was used for performance verification and space environment test such as thermal vacuum after developing Dehop/Rehop Transponder.

• Journal of Ocean Engineering and Technology
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• v.36 no.2
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• pp.132-142
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• 2022

We investigate the performance of multi-body wave energy converters (WECs). This investigation considers multiple scattering of water waves by the buoys of a WEC under the generalized mode approach. Predominantly, the effect of a WEC's configuration on its energy extraction is studied in this research. First, single-row terminator and single-column attenuator arrays of vertical cylinders have been studied. The performance of these attenuator arrays shows that the wall effect induced by the periodic buoys influences the wave propagation and energy extraction in these WECs. Further studies show that a single-row terminator array of vertical cylinders performs better than the corresponding single-column attenuator array. Subsequently, multi-row terminator arrays of vertical cylinders are investigated by conducting a parametric study. This parametric study shows that the hydrodynamic property of three resonance phenomena makes energy extraction efficiency drop down, and the magnitude of energy extracted oscillates between the resonance points in these WECs. Finally, a 4×8 terminator array of vertical cylinders is studied to determine the effect of various d_x (x-directional distance between adjacent rows) within this WEC on its performance. In particular, this study enforces at least two equal d_x values within the 4×8 terminator array of vertical cylinders. It shows that a small value of this d_x leads to better energy extraction efficiency in some of these various d_x arrays than that of a corresponding regular array with the same d_x.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.85-96
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• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2C
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• pp.209-216
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• 2009

The repeater for wireless broadband internet (Wibro) system using OFDM demands the short processing delay to eliminate inter-symbol interference resulted from the time delay greater than the guard time. Towards this, the total system delay of repeater is expected to be minimized as possible as it can without distorting signal quality. In general, the FIR-type of filter is commonly deployed as a channelization filter, but due to its large amount of coefficients for producing prerequisite filter response the excessive large time delay occurs. To withstand this problem, the paper proposes the method for designing IIR filter whose response almost identical to that of the original filter. Moreover, in order to linearize the phase response of the designed IIR filter, this paper also introduce the way of designing the all-pass filter to be cascaded works for linearizing phase response of the channelization as well as the de-channelization filter. To achieve the further improvement in linearization of the phase response and reduction of the overall complexity, this paper tries to transform the integrated IIR filter group into the structure in polyphase style. The computer simulation verifies that the integrated IIR filter group designed in this paper reveals the relatively short processing delay without harming the acceptible signal quality.