• Proceedings of the KIEE Conference
• /
• 1996.07a
• /
• pp.385-387
• /
• 1996

A novel two stage soft-switching ac-to-dc convener with power factor correction is proposed. The proposed convener provides zero-voltage-switching (ZVS) condition to main switch of boost pre-regulator without auxiliary switch. Comparing to the conventional two stage approach(ZVS-PWM boost rectifier followed by off-line ZVS dc-dc step down converter), the proposed approach is simple and reducing EMI noise problem. A new simple DC-linked energy feedback circuit provides zero-voltage-switching condition to boost pre-regulator without imposing additional voltage and current stresses and loss of PWM capability. Operational principle, analysis, control of the proposed converter together with the simulation results of 1KW prototype are presented.

• Journal of IKEEE
• /
• v.13 no.2
• /
• pp.208-215
• /
• 2009

The high efficiency power management IC(PMIC) with DT-CMOS(Dynamic Threshold voltage MOSFET) switching device for portable application is proposed in this paper. Because portable applications need high output voltages and low output voltage, Boost converter and Buck converter are embedded in One-chip. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. Boost converter and Buck converter, are based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 92.1% and 95%, respectively, at 100mA output current. And Step-down DC-DC converter in stand-by mode below 1mA is designed with LDO in order to achive high efficiency.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.10
• /
• pp.231-238
• /
• 2013

This paper describes a DC-DC converter IC for Flat Panel Displays. In case of operate LCD devices various type of DC supply voltage is needed. This device can convert DC voltage from 6~14[V] single supply to -5[V], 15[V], 23[V], and 3.3[V] DC supplies. In order to meet current and voltage specification considered different type of DC-DC converter circuits. In this work a negative charge pump DC-DC converter(-5V), a positive charge pump DC-DC converter(15V), a switching Type Boost DC-DC converter(23V) and a buck DC-DC converter(3.3V). And a oscillator, a thermal shut down circuit, level shift circuits, a bandgap reference circuits are designed. This device has been designed in a 0.35[${\mu}m$] triple-well, double poly, double metal 30[V] CMOS process. The designed circuit is simulated and this one chip product could be applicable for flat panel displays.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.9 no.4
• /
• pp.372-380
• /
• 2004

This paper proposes a single-power-stage high frequency resonant AC-DC converter with high power factor using ZVS(Zero Voltage Switching), and integrates a conventional converter with two stage into single stage converter. Input power factor is possible to be improved as a high power factor because inductor for power factor correction(PFC) is connected in input and converter is operated in discontinued current mode(DCM) with constant duty cycle and variable switching frequency. The conventional converter with two stage need to add a switch in order to control a power factor, but single stage converter have a advantage that system is simple and cost is down, confidence is improved, etc. This paper described a operation principle and characteristic analysis for single stage AC-DC converter with high power factor and have evaluated characteristic values by using normalized parameter. We make a experimental equipment using MOSFET as a switching device on the basis of characteristic values obtained from characteristic evaluations and we conform a rightfulness of theoretical analysis by comparing theoretical waveforms and experimental waveforms.

• Journal of the Korean Society for Precision Engineering
• /
• v.25 no.11
• /
• pp.83-89
• /
• 2008

The Effect of Space Velocity(SV) on NOx conversion rate was performed to develop NOx reduction after-treatment system. SV is calculated from engine exhaust gas volume and SCR catalyst volume. Found the Urea injection duty of maximum efficiency for NOx conversion if increase SV, NOx Conversion rate is down. Especially, when SV is more than $110,000h^{-1}$, NOx conversion rate decrease suddenly. Same case, if SV is lower than $40,000h^{-1}$, NOx conversion rate is down. Also, the characterization of Urea-SCR system was performed. Three candidate injectors for injecting Urea were tested in terms of 속 injection rate and NOx reduction rate. The performances of SCR catalytic converter on temperature were investigated. The performance of Urea-SCR system was estimated in the NEDC test cycle with and without EGR. It was found that nozzle type injector had high NOx conversion rate. SCR catalytic converter had the highest efficiency at the temperature of $350^{\circ}C$. EGR+Urea-SCR system achieved NOx reduction efficiency of 73% through the NEDC test cycle.

• Journal of the Microelectronics and Packaging Society
• /
• v.7 no.3
• /
• pp.19-25
• /
• 2000

In this paper, we describe RF receiver module for IMT-2000 handset with 5 MHz channel bandwidth. The fabricated RF receiver module consists of Low Noise Amplifier, RF SAW filter, Down-converter, If SAW filter, AGC and PLL Synthesizer. The NF and IIP3 of LNA is 0.8 dB, 3 dBm at 2.14 GHz, conversion gain of down-converter is 10 dB, dynamic range of AGC is 80 dB, and phase noise of PLL is -100 dBc at 100 kHz. The receiver sensitivity is -110 dBm, adjacent channel selectivity is 48 dBm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.11a
• /
• pp.435-439
• /
• 2002

This paper describes a design and fabrication of an electronic ballast for 70[W] ceramic discharge metal halide lamps. The proposed ballast is composed of a rectifier, an active power factor correction circuit (PFC), a half-bridge inverter, a LC resonant circuit and a microprocessor. The developed ballast also includes a specially designed time circuit which provides reignition of lamps. Running frequency of the ballast is set at 40[kHz] to avoid acoustic-resonance and flickering. From the experimental results, input power factor and efficiency of the ballast are estimated 99.8[%] and 93.1[%)] respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.1
• /
• pp.273-276
• /
• 2005

This paper presents an electronic ballast using a step down converter, a low frequency inverter for high pressure discharge lamp. The proposed ballast is composed of a full-wave rectifier, a step down converter operated as a current source with power regulation and a low frequency inverter with ignition circuit. The ignition circuit generates high voltage pulse of 1${\sim}$2[kV] peak, 130[Hz]. Moreover, it is able to reignite at regular intervals by protective circuit. As experimental results on the test, lamp voltage, current and consumption power are measured 132.5[V], 7.6[A] and 1,005[W], respectively. It was confirmed that the designed ballast operate the lamp with a constant power.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.1
• /
• pp.804-807
• /
• 2005

Design Up/Down converters which use Digital IF(Intermediate Frequency) techniques from the present paper, against hereupon performance the criticism. The reason which uses Digital IF techniques is configured of passive elements and the positions IF frequency domains are fixed and they do not use in the position one frequency but, the external fringe land of the board which comes to be configured with Digital IF without from the communication frequency domain which is various there to be a flexibility, the use was under possibility. Like this configuration compares in analog Heterodyne mode of existing and it has the performance upgrade which is excellent it shows a high flexibility.

• Journal of the Semiconductor & Display Technology
• /
• v.20 no.3
• /
• pp.71-76
• /
• 2021

Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.