• 대한조선학회 특별논문집
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• 대한조선학회 2007년도 특별논문집
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• pp.99-106
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• 2007

The IACS Common Structural Rules are to be applied for double hull tanker of more than 150m length with contracted after 1 April 2006. The objectives of the rules are to make more robust, safer ship and to ensure transparency of the technical background. In compliance of CSR, we had carried out prescriptive rules scantling determination and 3-D hold FE analysis of AFRAMAX TANKER. Prescriptive rules scantling determines the minimum required scantling, hull-girder longitudinal bending and shear strength, hull girder ultimate strength, local strength of plate and stiffener, strength of primary supporting member and fatigue assessment of the longitudinal stiffener end connections to the transverse bulkhead. 3-D hold FE analysis assesses the structural adequacy of the vessel's primary hull structure and major supporting members using yielding and buckling failure modes. So we could verify the strength assessment of AFRAMAX TANKER applied CSR.

• 대한조선학회논문집
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• 제30권2호
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• pp.123-131
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• 1993

오늘날 과학은 놀랍게 발전하고 있고, 과학문명의 성상은 인류의 위대한 업적 중 하나로 높게 평가되어진다. 그러나 한편, 이러한 발전은 새로운 문제를 유발케 되었는데 즉, 지구환경 오염을 가져오게 된 것이다. 이 지구환경 오염의 현상은 지구를 황폐케 할 뿐 아니라, 인간 생존권조차 위협케 되었다. 지난 1970년대로부터 유조선의 건조가 가속화되면서 전 세계적으로 해상환경오염방지에 대한 관심이 높아지면서 급기야 IMO에서 유조선에 대한 이중선체 구조의 의무화를 규정화 하였다. 이러한 시대적 배경을 통하여 당사에서는 미래 선박으로서 초대형 이중선체 유조선을 개발케 되었고, 본고에서는 각종 국제규정을 만족시키는 300K 이중선체 유조선 개발 내용을 소개하며, 특히 화물창부에 대한 구조배치 및 직접구조계산을 수행한 내용을 소개코져 한다.

• 한국신뢰성학회지:신뢰성응용연구
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• 제10권1호
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• 전자공학회논문지C
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• 제34C권6호
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• pp.37-43
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• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• 한국의상디자인학회지
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• 제10권1호
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• pp.99-116
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• 2008

This study reviewed pertinent literature and examined relics of manggon(a headband worn to hold a man's topknot hair in place), donggot(a topknot pin), and chigwan(a topknot cover). Before the modernized short hair style, wearing a gat was an important custom. Therefore, manggon, which was used to hold a man's hair in place under the gat, was considered an essential part of the man's official dress code. Donggot is a pin that held the topknot hair in place. It was a must have for a married man, like the binyeo, a lod-like hairpin, for a married woman. Unlike gwanja, it had nothing to do with official rank, but materials were of a variety of materials, including jade and gold. The structure of the donggot was studied in three parts-head, neck and body. Major forms for the head include the mushroom, bean and ball. Bullet and half-cut bullet forms were also found. Forms for the neck include straight-neck and curved-neck. A neck with a belt around a double chin was also found. Forms for the body include the tetrahedron, octahedron and cylinder. The most popular form for silver and white bronze donggot heads was the mushroom, followed by bean and pile forms. Chigwan is also called chipogwan, chichoal, choalgyesogwan, noingwan and sangtugwan. In poetry it was called chichoal, and it used to be called taegogwan in the past as well. Chigwan was so small that it managed to hold a topknot. According to confucian custom in the Joseon period, by wearing chigwan, men didn't display their bare topknot even when they didn't dress up. When they went out, they wore another official hat over the chigwan.

• 대한화학회지
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• 제36권5호
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• pp.674-678
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• 1992

전기저항이 큰(묽은) 용액에서도 금속전극의 이중층 전기용량을 전위와 시간의 변화에 따라 연속적으로 정확신속하게 측정할 수 있는 간단한 기기를 설계제작하였다. 주사전위에 작은 진폭의 삼각파를 겹칠 때 정전용량의 응답으로 주어지는 구형파를 관찰하면서 용액의 비보상 저항을 보정하여 평평한 부분을 얻고 이부위의 진폭을 샘플-홀드 회로로 채취하여 기록한다. 샘플링 위치와 기간의 조절가능 기능과 저잡음 대책을 마련하여 삼각파의 진폭을 7mV까지 낮출 수가 있어 페러데이 임피던스 영향을 줄일 수가 있었다. 몇가지 경우에 대한 성능 실험을 통해 응용성과 한계를 고찰하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 춘계학술대회 논문집 전기설비전문위원
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• pp.66-70
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• 2006

Frequency is an important operating parameter of a power system. Electric power systems sustain transient frequency swings whenever the balance between generation and load does not no longer hold. To cope with this Constraints, il requires an accurate and high speedy frequency deviation estimation technique and suitable adjustment to obtain the power system energy balance. This paper describes the design, computational aspects and implementation of an iterative technique for measuring power system. The rate change of the phase angle is used for estimation. To confirm the validity of the proposed algorithm, the simulation studies carried out on a typical 154[KV] double T/L system by using EMTP software. Some test results are presented in the paper.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 전문대학교육위원
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• pp.68-71
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• 2004

Frequency is an important operating parameter of a power system. Electric power systems sustain transient frequency swings whenever the balance between generation and load does not no longer hold. To cope with this Constraints, it requires an accurate and high speedy frequency deviation estimation technique and suitable adjustment to obtain the power system energy balance. This paper describes the design, computational aspects and implementation of an iterative technique for measuring power system. The rate change of the phase angle is used for estimation. To confirm the validity of the proposed algorithm, the simulation studies carried out on a typical 154[KV] double T/L system by using EMTP software. Some test results are presented in the paper.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술대회 논문집 전문대학교육위원
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• pp.92-95
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• 2003

Frequency is an important operating parameter of a power system. Electric power systems sustain transient frequency swings whenever the balance between generation and load does not no longer hold. To cope with this Constraints. it requires an accurate and high speedy frequency deviation estimation technique and suitable adjustment to obtain the power system energy balance. This paper describes the design, computational aspects and implementation of an iterative technique for measuring power system. The rate change of the phase angle is used for estimation. To confirm the validity of the proposed algorithm, the simulation studies carried out on a typical 154[KV] double T/L system by using EMTP software. Some test results are presented in the paper.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.975-978
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• 2003

본 논문에서는 비디오 신호 인터페이스를 위해 10비트 50MHz ADC 를 설계하였으며 DCL(digital-error correction logic)을 갖는 3-3-3-4 구조의 파이프라인 방식을 사용하였다. SHA(sample and hold amplifier)와 MDAC (multiplying digital-to-analog converter)에 쓰이는 증폭기는 높은 이득을 갖도록 gain-boosting 기법을 적용하였으며, 전력소모와 면적을 줄이기 위해 capacitor scaling 기법을 적용하였다. 본 ADC 는 0.35 μm double-poly four-metal n-well CMOS 공정으로 설계 및 제작하였으며, 전체 회로는 3.3V 단일 전원 전압에서 동작하도록 설계하였다. 측정 결과 5MHz 의 입력을 인가하였을 때 SNDR 은 56.7dB, 전체 전력 소모는 112mW 이며, 입출력 단의 패드를 포함한 전체 칩 면적은 2.6mm×2.6mm이다.