• The Journal of the Korea Contents Association
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• v.14 no.2
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• pp.475-481
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• 2014

The aim of this work was to develop the gamma camera system for small animal gamma imaging and environmental radiation monitoring imaging using a parallel hole collimator and pinhole collimator. The small gamma camera system consists of a CsI(Tl) scintillation crystal with 6 mm in thickness and $50{\times}50mm$ in area coupled with a Hamamatsu H8500C PSPMT, are resistive charge divider, pre-amplifiers, charge amplifiers, nuclear instrument modules (NIMs), an analog to digital converter and a computer for control and display. We have developed a radiation monitoring system composed of a combined pinhole gamma camera and a charge-coupled devices (CCD) camera. The results demonstrated that the parallel hole collimator and pinhole collimator gamma camera designed in this study could be utilized to perform small animal imaging and environmental radiation monitoring system. Consequently in this paper, we proved that our gamma detector system is reliable for a gamma camera which can be used as small animal imaging and environmental radiation monitoring system.

• Journal of Advanced Navigation Technology
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• v.15 no.1
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• pp.97-103
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• 2011

This paper presents a dual-band balanced mixer using nonlinear phase characteristic of composite right/left-handed (CRLH) transmission line. This metamaterial structure provides low LO leakage and high RF to LO isolation without additional filters for LO and RF path. The balanced mixer consists of balun and Wilkinson divider with dual-band characteristic of unit-cell which behaves like a CRLH metamaterial. Experimental results are used to verify the proposed metamaterial functions. The balanced mixer design results in an operating frequency of 870 MHz and 1660 MHz with an optimum mixer conversion loss of 15.2 dB at 870 MHz and 21.2 dB at 1660 MHz.

• Journal of Advanced Navigation Technology
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• v.21 no.1
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• pp.66-71
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• 2017

This paper describes implementation of a 165 MHz, 5 kW RF high power amplifier (HPA) for particle accelerator applications. The HPA consists of a drive amplifier for main amplifiers driving, sixteen 600 W class-AB push-pull power amplifier pallets and Wilkinson power divider/combiner using lumped LC components, which are divided/combined power amplifier pallet outputs. To detected the amplifier circuit of normal and reflected output power conditions, we used a bidirectional coupler. To radiate heat of main power amplifier, we were used an water-cooled copper plates to go through a water for radiation of heat. The HPA of center frequency 165 MHz has archived an efficiency of 62.5 % at 5 kW of power level experimentally.

• Journal of the Korean Applied Science and Technology
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• v.36 no.4
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• pp.1410-1419
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• 2019

In this research, it is to find a method that frost does not form on the outdoor unit to develop a heat pump capable of heating in cold regions. For this reason, we produced an incubator capable of creating an environment of -25℃, and constructed an experimental apparatus so that experiments in the room were possible. However, it is necessary to grasp the characteristics of the air reaching the front of the heat pump outdoor unit installed in the experimental apparatus, and flow analysis was performed using ANSYS CFX, which is general-purpose software. As a result, the flow velocity of the air reaching the front of the outdoor unit in the outdoor unit chamber in the entire region of the simulation conditions (5.0 to 7.5 m/s) has many differences in the upper and lower portions, resulting in a natural state. It turned out that the condition can not be satisfied. Therefore, it is determined that it is necessary to additionally install a frequency divider at the front of the outdoor unit to make the flow velocity constant.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2267-2272
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• 2009

The six-port direct conversion receiver front-end that is comprised of a carrier recovery and a phase shifter, which gets the same structure with six-port phase correlator using the multi-layer coupled line, was designed and fabricated in this paper. The six-port element that is comprised of the power divider and the hybrid coupler is designed by multi-layer coupled line structure. The multi-coupled structure is utilized as the basic structure in receiver phase correlator, carrier recovery circuit and phase shifter. The receiver front-end with the same multi-layer coupled line structure for the receiver elements shows the simple structure and no difficulty in integration. The fabricated multi-layer coupled six-port receiver front-end re-generates the carrier signal with a constant phase and demodulates the PSK transmission signal.

• Proceedings of the Korea Water Resources Association Conference
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• 2008.05a
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• pp.2056-2060
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• 2008

도시하천의 오염원은 점오염원과 비점오염원으로 분류되어 점오염원은 하천유입 전에 차집하여 하수처리장에서 처리하는 체계가 갖추어져 있으나 전체 오염부하량의 $30%{\sim}40%$ (BOD기준)로 추정되는 비점오염원은 차집되거나 처리되지 않고 그대로 하천에 유입되고 있는 실정이다. 비점오염원은 불특정 오염원으로서 지표의 오염물질이나 합류식 하수관거의 하수가 강우에 의해 발생한 유출과 함께 하천으로 유입(CSOs)되어 우천 시에 하천을 오염시키는 가장 큰 원인이 되고 있으므로 이의 저감하기 위한 효과적인 비점오염원 관리방안이 요구된다. 본 연구에서는 대상유역인 부산광역시에 위치한 온천천 유역을 주요토구별 43개 유역으로 구분하여 SWMM(Storm Water Management Model)을 구축하였고 개별 토구에 Divider를 설치하여 일정 차집량을 초과하는 유량은 처리장으로 유입되는 것으로 모의하였다. 장치형 처리시설은 농도에 따라 일정효율을 가지고 처리시설의 임계유량을 초과하는 경우는 미처리되어 방류되는 것으로 가정하였으며 처리장으로 차집된 유량도 처리장의 시간최대 유량을 초과하는 유량은 간이처리 후 방류되는 것으로 가정하여 시나리오에 따라 모의하였다. 각 토구별로 처리시설을 설치한 경우의 처리효율과 차집비율을 증가시켜 처리장에서 일괄처리하는 경우의 처리효율을 차집비율별로 검토하여 최적의 차집비율을 검토하였다. 또한 오염원 관리측면의 면적당 축적부하량 저감과 발생량 관리측면의 토구의 차집비율 증가 및 토구에 대한 처리시설 설치비율에 따른 효율을 검토하여 처리효율, 오염원 저감 및 차집비율에 대한 상관관계를 도출하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.19-25
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• 2017

This paper deals with integer factorization of two prime p,q of SHA-256 secure hash value n for Bit coin mining. This paper proposes an algorithm that greatly reduces the execution time of Pollard's rho integer factorization algorithm. Rho(${\rho}$) algorithm computes $x_i=x^2_{i-1}+1(mod\;n)$ and $y_i=[(y^2_{i-1}+1)^2+1](mod\;n)$ for intial values $(x_0,y_0)=(2,2)$ to find the factor 1 < $gcd({\mid}x_i-y_i{\mid},n)$ < n. It however fails to factorize some particular composite numbers. The algorithm proposed in this paper applies multiple initial values $(x_0,y_0)=(2^k,2^k)$ and ($2^k,2$), $2{\leq}k{\leq}10$ to the existing Pollard's Rho algorithm. As a results, the proposed algorithm achieves both the factorization of all the composite numbers and the reduction of the execution time of Pollard's Rho by 67.94%.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.99-105
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• 2014

A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.967-973
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• 2009

In this paper, X-band satellite communication oscillator of double phase locked is implemented by constructing a couple of phased-locked loop, and then we have analyzed the phase noise of designed PLL-DRO. The designed phase-locked oscillator is consist of series feedback DRO, frequency divider, phase detector, loop filter and programmable PLL-IC. By dividing oscillation frequency of 12.6 GHz into two frequencies, it exhibits output power of 15.32 dBm at 6.3 GHz. Phase noises of implemented oscillator are -81 dBc/Hz@100Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz and -140.49 dBc/Hz@1 MHz respectively. These indicate excellent stable operation of oscillator and very good phase noise characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.49-55
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• 2005

In this paper, the phase locked harmonic oscillator(PLHO) using the analog PLL(Phase Locked Loop) is designed and implemented for a wireless LAN system. The harmonic oscillator is consisted of a ring resonator, a varactor diode and a PLL circuit. Because the fundamental fiequency of 8.5 GHz is used as the feedback signal for the PLL and the 2nd harmonic of 17.0 GHz is used as the output, a analog frequency divider for the phase comparison in the PLL system can be omitted. For the simple PLL circuit, the SPD(Sampling Phase Detector) as a phase comparator is used. The output power of the phase locked harmonic oscillator is 2.23 dBm at 17 GHz. The fundamental and 3rd harmonic suppressions are -31.5 dBc and -29.0 dBc, respectively. The measured phase noise characteristics are -87.6 dBc/Hz and -95.4 dBc/Hz at the of offset frequency of 1 kHz and 10 kHz from the carrier, respectively.